Murata Manufacturing Co., Ltd.

Koninklijke Philips Corporation N.v.

U.S. Philips Corporation

Nxp B.v.

Integrated Device Technology, Inc.

Murata Integrated Passive Solutions

Stéphane Bouvier

Nicolas Normand

Emmanuel Lefeuvre

Frédéric Voiron

Florent Lallemand

Julien El Sabahy

Yasuhiro Murase

Larry Buffle

Emmanuel Savin

Jean-René Tenailleau

Yohei Yamaguchi

Luis Rolindez

Yves Aubry

Marc Boiron

Jean-Philippe Audic

Sylvain Dumont

David Denis

Sébastien Iochem

A current path is provided through an interposer to ground a grounding pattern associated with a transmission line, by exploiting an interposer substrate that has a high-resistivity portion at a first surface and a low-resistivity portion extending from the high-resistivity portion to a second surface of the interposer. Moreover, a set of blind via-holes comprising electrically-conductive material extend from the first surface of the interposer substrate through the high-resistivity portion and into the low-resistivity portion. Top-to-bottom connection can be made using the conductive material in the blind vias and using the low-resistivity portion of the substrate, while the high-resistivity portion of the substrate impedes current leakage from the transmission line to the second surface of the substrate. The number and dimensions of the blind via-holes control the impedance of the grounding pattern relative to the transmission line's characteristic impedance.

Through-interposer grounding using blind vias

A semi-conductor structure with selective bottom terminal contacting is described. The semiconductor device comprises a first metal layer disposed over a substrate; a conductive layer disposed over the first metal layer; and a second metal layer disposed over the conductive layer, the second metal layer embedding a porous structure comprising a plurality of pores that extend substantially perpendicularly from a top surface of the porous structure toward the conductive layer, wherein only a subset of the plurality of pores open onto the conductive layer.

Semiconductor structure with selective bottom terminal contacting

An electronic device and a method for manufacturing an electronic device. The electronic device includes: a board equipped with a pair of differential transmission lines, each line of the pair having an opening extending between two line terminals; and a capacitor module that includes: a base; and two 3D capacitors supported by the base, each 3D capacitor comprising two capacitor terminals respectively connected to the two line terminals of one line of the pair of transmission lines.

Electronic device with differential transmission lines equipped with capacitors supported by a base, and corresponding manufacturing method

RC-network components that include a substrate and capacitor having a thin-film top electrode portion at a surface on one side of the substrate. The low ohmic semiconductor substrate is doped to contribute 5% or less to the resistance of the RC-network component. The resistance provided in series with the capacitor is controlled by providing a contact plate, spaced from the thin-film top electrode portion by an insulating layer, and a set of one or more bridging contacts passing through openings in the insulating layer. The bridging contacts electrically interconnect the thin-film top electrode portion and the contact plate. Different resistance values can be set by appropriate selection of the number of bridging contacts. The openings are elongated thereby reducing temperature concentration at their periphery. Correspondingly, the bridging contacts have an elongated cross-sectional shape.

Contact structures in RC-network components

An electronic product having a first capacitor and a second capacitor, where the electronic product includes a semi-conductor substrate having a bottom electrode region of the first capacitor and a bottom electrode region of the second capacitor; a first dielectric layer having a first thickness arranged above the bottom electrode region of the first capacitor; a second dielectric layer having a second thickness arranged above the bottom electrode region of the second capacitor, the first thickness and the second thickness being different; a top electrode region of the first capacitor arranged above the bottom electrode of the first capacitor and above the first dielectric layer; and a top electrode region of the second capacitor arranged above the bottom electrode of the second capacitor and above the second dielectric layer.

Method for forming an electronic product comprising two capacitors having different dielectric thicknesses, and corresponding electronic product

An electrical device that includes a substrate; a 3D capacitor including a capacitor dielectric region of a dielectric material, a capacitor electrode region of a conductive material, the capacitor dielectric region and the capacitor electrode region being arranged at least partially inside a cavity extending in the substrate from a top face of the substrate; and a surrounding through opening in the substrate and which surrounds a surrounded substrate region, the 3D capacitor being outside of the surrounded substrate region, the surrounding through opening extending from the top face to a bottom face of the substrate, wherein inside the surrounding through opening a surrounding dielectric region of the dielectric material and a surrounding conductive region of the conductive material are arranged.

Electrical device comprising a 3D capacitor and a region surrounded by a through opening

The invention concerns an implementable semiconductor device that includes an electrode configured to be in contact with biological tissue and at least one capacitor, and wherein the capacitor includes a capacitor electrode having a first surface facing and in contact with the electrode configured to be in contact with biological tissue.

Implementable semiconductor device, comprising an electrode and capacitor, and corresponding manufacturing method

An electronic product that includes a component having a first electrode with a first surface and a pillar extending from the first surface in a first direction, the pillar having three protrusions, the three protrusions forming angles of about 120 degrees with each other around a central line of the pillar where the three protrusions meet, and the three protrusions being bent so that the pillar has a triskelion cross-section in a plane perpendicular to the first direction.

Electronic product comprising a component having triskelion-pillars, and corresponding fabrication method

An integrated resistor-capacitor (RC) structure () is disclosed. The integrated RC structure includes a vertical capacitor () and a resistive element () disposed above the capacitor. The integrated RC structure uses a low ohmic substrate () to ensure a good ground return path for the capacitor. Further, a resistivity of the substrate is configured such that a top plate () of the capacitor provides a reference ground above a predefined frequency. The impedance of the resistive element () is matched, relative to the reference ground, to a predetermined resistance. As such, the resistance of the resistive element () can be controlled to provide an impedance controlled RC structure over a range of operating frequencies.

Distributed RC termination

An integrated electronic component for broadband biasing that includes a monolithic substrate, a capacitor structure arranged in a trench network that extends into the substrate, and a continuous track of an electrically conducting material arranged in a crater that is formed in the substrate. The continuous track has one or several turns that have decreasing turn sections, and that are supported by a slanted peripheral wall of the crater for forming an inductor.

Integrated electronic component suitable for broadband biasing

Systems and methods for protecting an analog-to-digital converter (ADC) are provided. The provided systems and methods utilize comparators in a circuit of a stage of the ADC to compare a reference signal to an input signal and output one or more maximum signals when the input signal exceeds the reference signal. A decoder in the stage of the ADC may output a reset signal to another circuit in the stage of the ADC when a predetermined number of the maximum signals are received. When the other circuit receives the reset signal, the ADC may enter a protection mode to protect the ADC by ensuring that the excessive input signal is not propagated to subsequent stages.

Protection for analog to digital converters

The invention relates to an ESD protection device comprising: a first contact () and a second contact (), and an electrical node (); a bipolar transistor () having a base, an emitter, and a collector, the base and emitter forming a base-emitter junction, the base and collector forming a base-collector junction, the emitter being connected to the first contact (), the collector being connected to the second contact (), the base being connect to the electrical node (); a first diode () connected between the electrical node () and the first contact (), the first diode () comprising a first junction arranged in the same direction as the base-emitter junction, and&#x2014;a second diode () connected between the electrical node () and the second contact (), in anti-series with the first diode () on a path from the first contact () to the second contact (), the second diode () comprising a second junction arranged in the same direction as the base-collector junction, wherein the bipolar transistor () is dimensioned to have such a current gain (&#x3b2;) that the voltage-current characteristic of the ESD protection device, measured between the first () and second contact (), exhibits a voltage snap-back effect (SNP) at its trigger voltage (Vtrig). The voltage snap-back effect (SNP) results in a lower clamping voltage of the ESD protection device. The invention further relates a semiconductor device and an integrated system in a package comprising said ESD protection device.

ESD-protection device, a semiconductor device and integrated system in a package comprising such a device

This device finds interesting applications in the field of interface circuits for optical fibers. There is proposed in this circuit to utilize a symmetrical amplifier ( ) to which an automatic gain control circuit ( ) is added which is insensitive to variations of the offset voltage of this amplifier. This control circuit ( ) comprises peak detectors which give the best results in a circuit of this type intended for processing signals at very high frequencies.

Device comprising a symmetrical amplifier

Modulation device of the pulse width of very high-frequency signals

A control circuit controls the power supply to an electric motor and, comprises a power transistor NM of the NMOS type and a power transistor PM of the PMOS type arranged between two supply terminals VCC and GND, their intermediate node forming an output coupled to a coil Ei of the motor. The well B of the transistor PM is coupled to supply terminal VCC via an isolation diode ID, which has its anode connected to supply terminal VCC and has its cathode connected to the well B. The isolation diode ID ensures that the coil Ei is not short-circuited by the parasitic drain-well diode D of the transistor PM in case of a sudden power failure.

Growing community of inventors

Cairon, France

Stéphane Bouvier