Hitachi Energy Ltd

International Business Machines Corporation

Hitachi Energy Switzerland Ag

Abb Power Grids Switzerland Ag

Stephan Wirths

Lars Knoll

Heinz Schmid

Kirsten Emilie Moselund

Andrei Mihaila

Marco Bellini

Vinoth Sundaramoorthy

Benedikt F Mayer

Gianpaolo Romano

An insulated gate structure includes a wide bandgap material layer having a channel region of a first conductivity type. A gate insulating layer is arranged directly on the channel region and has a first nitride layer that is arranged directly on the channel region. The gate insulating layer has a concentration of carbon atoms that is less than 10atoms/cmat a distance of 3 nm from an interface between the wide bandgap material layer and the first nitride layer. An electrically conductive gate electrode layer overlies the gate insulating layer so that the gate electrode layer is separated from the wide bandgap material layer by the gate insulating layer.

Insulated gate structure, wide bandgap material power device with the same and manufacturing method thereof

A SiC transistor device includes a SiC semiconductor substrate, a SiC epitaxial layer formed on the top surface of the SiC semiconductor substrate, a source structure formed in the top surface of the SiC epitaxial layer, a source contact structure electrically coupled to the top surface of the source structure, and a gate structure that includes a gate dielectric, a metal gate, and a gate insulation. A first backside metal contact is formed on the bottom surface of the SiC semiconductor substrate, a stress inducing layer is formed on the first backside metal contact, and a second backside metal contact is formed on the stress inducing layer.

Strain enhanced SiC power semiconductor device and method of manufacturing

A silicon carbide transistor device includes a silicon carbide semiconductor and a silicon carbide epitaxial layer formed at a top surface of the substrate. A source structure is formed in a top surface of the silicon carbide epitaxial layer and includes a p-well region, a n-type source region and a p-type contact region. A source contact structure is formed over and electrically connected to a top surface of the source structure. A planar gate structure includes a gate dielectric and a gate runner adjacent a p-type channel region. The gate dielectric covers the channel region, at least part of the source structure and at least part of the source contact structure. The gate runner is electrically insulated from the channel region and the source structure and the source contact structure by the gate dielectric and overlaps the channel region.

Silicon carbide transistor device

Disclosed is a vertical silicon carbide power MOSFET with a 4H-SiC substrate of n+-type as drain and a 4H-Si C epilayer of n−-type, epitaxially grown on the 4H-SiC substrate acting as drift region and a source region of p++-type, a well region of p-type, a channel region of p-type and a contact region of n++-type implanted into the drift region and a metal gate insulated from the source and drift region by a gate-oxide. A high mobility layer with a vertical thickness in a range 0.1 nm to 50 nm exemplarily in the range of 0.5 nm to 10 nm is provided at the interface between the 4H-SiC epilayer and the gate-oxide.

Vertical silicon carbide power MOSFET and IGBT and a method of manufacturing the same

A plasmonic quantum well laser may be provided. The plasmonic quantum well laser includes a plasmonic waveguide and a p-n junction structure extends orthogonally to a direction of plasmon propagation along the plasmonic waveguide. Thereby, the p-n junction is positioned atop a dielectric material having a lower refractive index than material building the p-n junction, and the quantum well laser is electrically actuated. A method for building the plasmonic quantum well laser is also provided.

Growing community of inventors

Thalwil, Switzerland

Stephan Wirths