Infineon Technologies Ag

Applied Materials, Inc.

Qimonda Ag

Stephan Wege

Markus M Kirchhoff

Mirko Vogt

Maik Stegemann

Peter Lahnor

Hans-Peter Sperlich

Ralf Zedlitz

Momtchil Stavrev

Dirk Drescher

Andreas Klipp

Joerg Dreybrodt

Ajay Kumar

Rolf Weis

Kallol Bera

Manfred Schneegans

Volker Strutz

Hans-Peter Moll

Anisul Haque Khan

Dirk Manger

Dragan Valentin Podlesnik

Kenny Linh Doan

Zvonimir Gabric

Mihel Seitz

Peter Moll

Michael Rogalli

Ines Uhlig

Oswald Spindler

Oliver Genz

Subhash Deshmukh

Virinder Grewal

Christoph Noelscher

Sharma V Pamarthy

Achim Neu

Ulrike Bewersdorff-Sarlette

Moritz Haupt

Jens Zimmermann

Uwe Schilling

Barbara Schmidt

Alexander Reb

Alexander Michaelis

Carsten Fuelber

Momtchill Stavrev

Stephan Machill

Wolfgang Jäger

Axel Henke

Tobias Mayer-Uhma

Martin Schneegans

Cornelia Klein

Kerstin Krahl

R&uuml;diger Uhlmann

Falko Schlenkrich

Hans Glawischnig

Roger-Michael Wolf

Guenther Czech

A method of preparing a coating solution, comprising the steps of providing a first solution comprising a lower alcohol; a polyethylene glycol; a complexing agent; and water; providing a second solution comprising a higher alcohol; and at least one metal alkoxide, wherein the metal in said at least one metal alkoxide is selected from the group consisting of zirconium, aluminium, titanium, tantalum and yttrium; forming a sol-gel solution by mixing said first and second solutions and thereby hydrolyzing said at least one metal alkoxide to a metal oxide and an alcohol; forming a concentrated solution by removing said lower alcohol and the alcohol resulting from the hydrolysis of said at least one metal alkoxide; and forming a coating solution by adding a medium alcohol to said concentrated solution.

Method of preparing a coating solution and a corresponding use of the coating solution for coating a substrate

High aspect ratio contact openings are etched while preventing bowing or bending of the etch profile by forming a highly conductive thin film on the side wall of each contact opening. The conductivity of the thin film on the side wall is enhanced by ion bombardment carried out periodically during the etch process.

Method of preventing etch profile bending and bowing in high aspect ratio openings by treating a polymer formed on the opening sidewalls

In one aspect, a method of forming a structure on a substrate is disclosed. For example, the method includes forming a first mask layer and a second mask layer, modifying a material property in regions of the first and second mask layers, and forming the structure based on the modified regions.

Method for forming a structure on a substrate and device

An apparatus includes a plasma process chamber and a support element capable of supporting a substrate inside the plasma process chamber. At least one plasma control element is placed adjacent to a peripheral portion of the support element such that the plasma control element is capable of influencing a plasma inside the plasma process chamber if an electric field is applied thereto. At least one voltage generator is connected to the plasma control element. The plasma control element is movable inside the process chamber such that it can be set to any of at least two different positions.

Apparatus for processing a substrate

A carbon hard mask layer is applied to a substrate to be patterned by means of a plasma-enhanced deposition process in such a manner that it has a hardness comparable to that of diamond in at least one layer thickness section. During the production of this diamond-like layer thickness section, the parameters used in the deposition are set in such a manner that growth regions which are produced in a form other than diamond-like are removed again in situ by means of subsequent etching processes and that diamond-like regions which are formed are retained.

Photolithographic patterning process using a carbon hard mask layer of diamond-like hardness produced by a plasma-enhanced deposition process

The present invention provides a fabrication method for a semiconductor structure having the steps of providing a semiconductor substrate (); providing and patterning a silicon nitride layer () on the semiconductor substrate () as topmost layer of a trench etching mask; forming a trench () in a first etching step by means of the trench etching mask; conformally depositing a liner layer () made of silicon oxide above the resulting structure, which leaves a gap (SP) reaching into the depth in the trench (); carrying out a V plasma etching step for forming a V profile of the line layer () in the trench (); wherein the liner layer () is pulled back to below the top side of the silicon nitride layer (); an etching gas mixture comprises CF, Oand an inert gas is used in the V plasma etching step; the ratio (V) of CF/Olies between 2.5 and 3.5; and the selectivity of the V plasma etching step between silicon oxide and silicon nitride is at least 10.

Fabrication method for a semiconductor structure

A method for producing a semiconductor structure including preparing a semiconductor substrate, and generating a lower first, a middle second and an upper third masking layer on a surface of the semiconductor substrate. The method further includes forming at least one first window in the upper third masking layer, structuring the middle second masking layer using the first window for transferring the first window, structuring the lower first masking layer using the first window for transferring the first window, and enlarging the first window to form a second window. The method for further includes restructuring the middle second masking layer using the second window for transferring the second window, structuring the semiconductor substrate, using the structured lower third masking layer, restructuring the lower first masking layer using the second window, and restructuring the semiconductor substrate using the restructured lower third masking layer.

Method for production of a semiconductor structure

The present invention provides a method for fabricating a semiconductor structure having the steps of: providing a semiconductor substrate () made of silicon with a first hard mask layer () made of silicon oxide and an overlying second hard mask layer () made of silicon; providing a masking layer () made of silicon oxide above and laterally with respect to the second hard mask layer () made of silicon and above an uncovered edge region (RB) of the semiconductor substrate (); providing a photoresist mask () above the masking layer () with openings corresponding from trenches (DT) to be formed in the semiconductor substrate (); opening the masking layer () in a first plasma process using the photoresist mask (), the edge region (RB) being covered by a shielding device (AR); opening the first hard mask layer () and second hard mask layer () in a second and third plasma process; and forming the trenches (DT) in the semiconductor substrate () in a fourth plasma process using the opened first hard mask layer (); the edge region (RB) not being covered by the shielding device (AR) in the second to fourth plasma processes.

Method for fabricating a semiconductor structure

Process for producing an etching mask on a microstructure, in particular a semiconductor structure with trench capacitors, and corresponding uses of the etching mask which allow for extremely thin photoresist layers to be employed.

Process for producing an etching mask on a microstructure, in particular a semiconductor structure with trench capacitors, and corresponding use of the etching mask

A method for fabricating a semiconductor component includes: deposition of a polysilicon layer on a substrate, deposition of a precursor layer on the polysilicon layer, and deposition of a protective layer on the precursor layer. A crystalline transformation occurs in the precursor layer at a first temperature to form an electrode layer. The layers are patterned to form an electrode stack, and the polysilicon layer is oxidized at a second temperature such that no crystalline transformation occurs in the electrode layer.

Production method for a semiconductor component

A method for operating a plasma reactor to etch high-aspect-ratio features on a workpiece in a vacuum chamber. The method comprises the performance of an etch process followed by a flash process. During the etch process, a first gas is supplied into the vacuum chamber, and a plasma of the first gas is maintained for a first period of time. The plasma of the first gas comprises etchant and passivant species. During the flash process, a second gas comprising a deposit removal gas is supplied into the vacuum chamber, and a plasma of the second gas is maintained for a second period of time. The DC voltage between the workpiece and the plasma of the second gas during the second period of time is significantly less than the DC voltage between the workpiece and the plasma of the first gas during the first period of time.

Method for etching high-aspect-ratio features

The optimization of a CMP process provides the use of an auxiliary layer ( ) between a dielectric ( ) in the vicinity of patterned portions and a layer of a liner ( ). If the liner ( ) is perforated in the CMP process, then the undercutting of the liner ( ) by the chemical removal of the auxiliary layer ( ) simplifies the process overall. Advantages are significantly lower defect densities due to CMP scratches, fewer short circuits, fewer alignment errors.

CMP process

Doped polysilicon layers and layered polysilicon structures are produced, and the layers and layered structures are structured. The doping is distinguished by the fact that the doping compound is added as a process gas during the chemical vapor deposition of the polysilicon to define the doping profile. The feed of dopant to the process gas is stopped toward the end of the vapor deposition, with the result that a boundary layer of undoped silicon is deposited. As a result, a favorable surface quality and better adhesion to a neighboring layer is obtained. The structuring process comprises an at least three-step etching process in which a fluorine containing gas is used for etching in a first step, a chlorine-containing gas is used for etching in a second step and a bromine-containing gas is used for etching in a third step. The invention also encompasses wafers and semiconductor chips produced with the novel doping and/or structuring method.

CVD method of producing in situ-doped polysilicon layers and polysilicon layered structures

Metal/metal contacts are formed as part of a multilayer metallization in an integrated circuit on a semiconductor wafer. The application of an insulation layer on a metal level is followed by a lithography step using a photoresist mask to define contact holes on the insulation layer, followed by anisotropic etching of the insulation layer in order to produce the contact holes. Then, a chemical dry etch that removes the photoresist mask and a chemical-physical dry etch that removes organic impurities which accumulate during the chemical dry etch are successively carried out in a vacuum. Subsequently, a metal deposition step is carried out in order to fill the contact holes.

Method and device for producing a metal/metal contact in a multilayer metallization of an integrated circuit

A method for fabricating a trench isolation for electrically active components in a semiconductor component. A mask is applied to a semiconductor substrate. Subsequently, a trench having side walls is formed in the semiconductor substrate by performing a dry etching process using at least one etching gas such that during the dry etching process, polymers are produced that at least partly cover the side walls of the trench and thereby at least partially protect the side walls against an etching attack from the etching gas. The etching gas is provided with a compound that is selected from the group consisting of at least one hydrocarbon compound and a fluorinated hydrocarbon compound. The trench is filled with an insulating oxide.

Method for fabricating a trench isolation for electrically active components

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Dresden, Germany

Stephan Wege