Infineon Technologies Ag

Infineon Technologies Austria Ag

Stephan Voss

Hans-Joachim Schulze

Alexander Breymesser

Franz-Josef Niedernostheide

Frank Dieter Pfirsch

Francisco Javier Santos Rodriguez

Thomas Basler

Erich Griebl

Edward Fuergut

Helmut Oefner

Matthias Kuenle

Holger Huesken

Peter Tuerkes

Anton Mauder

Markus Zundel

Roman Baburske

Werner Schustereder

Martin Gruber

Bernhard Goller

Carsten Schaeffer

Andreas Moser

Thomas Kimmer

Joachim Mahler

Johannes Georg Laven

Roland Rupp

Oliver Haeberlen

Christian Philipp Sandow

Elmar Falck

Roman Roth

Wolfgang Scholz

Mathias Plappert

Philipp Seng

Sokratis Sgouridis

Daniel Pedone

Michael Knabl

Yvonne Gawlina-Schmidl

Andreas Huerner

Alexander Susiti

Oana Julia Spulber

Wolfgang Wagner

Shuhai Liu

Eva-Maria Hof

A device includes an interposer including an insulative layer between a lower metal layer and a first upper metal layer and a second upper metal layer, a semiconductor transistor die attached to the first upper metal layer and comprising a first lower main face and a second upper main face, with a drain or collector pad on the first main face and electrically connected to the first upper metal layer, a source or emitter electrode pad and a gate electrode pad on the second main face, a leadframe connected to the interposer and comprising a first lead connected with the first upper metal layer, a second lead connected with the source electrode pad, and a third lead connected with the second upper metal layer, and wherein an electrical connector that is connected between the gate electrode pad and the second upper metal layer is orthogonal to a first electrical connector.

Semiconductor device with improved performance in operation and improved flexibility in the arrangement of power chips

A method of forming a semiconductor device includes: forming a first semiconductor layer on a semiconductor substrate, the first semiconductor layer being of the same dopant type as the semiconductor substrate, the first semiconductor layer having a higher dopant concentration than the semiconductor substrate; increasing the porosity of the first semiconductor layer; first annealing the first semiconductor layer in an atmosphere including an inert gas; forming a second semiconductor layer on the first semiconductor layer; and separating the second semiconductor layer from the semiconductor substrate by splitting within the first semiconductor layer. Additional methods of forming a semiconductor device are described.

Methods for forming a semiconductor device having a second semiconductor layer on a first semiconductor layer

A semiconductor device and a method of manufacturing a semiconductor are provided. In an embodiment, a metallic layer may be formed over a semiconductor substrate. An anti-reflective layer may be formed over the metallic layer. A passivation layer may be formed over the anti-reflective layer. An opening may be formed in the passivation layer to expose the anti-reflective layer.

Semiconductor device protection using an anti-reflective layer

A method of forming a semiconductor device, including forming a first semiconductor layer on a semiconductor substrate, the first semiconductor layer being of the same dopant type as the semiconductor substrate, the first semiconductor layer having a higher dopant concentration than the semiconductor substrate, increasing the porosity of the first semiconductor layer, first annealing the first semiconductor layer at a temperature of at least 1050&#xb0; C., forming a second semiconductor layer on the first semiconductor layer and separating the second semiconductor layer from the semiconductor substrate by splitting within the first semiconductor layer.

Methods for forming a semiconductor device

A semiconductor package includes a die pad comprising a die attach surface, a first lead extending away from the die pad, one or more semiconductor dies mounted on the die attach surface, the one or more semiconductor dies comprising first and second bond pads that each face away from the die attach surface, and a distribution element that provides a first transmission path for a first electrical signal between the first lead and the first bond pad of the one or more semiconductor dies and a second transmission path for the first electrical signal between the first lead and the second bond pad of the one or more semiconductor dies. The distribution element comprises at least one integrally formed circuit element that creates a difference in transmission characteristics between the first and second transmission paths.

Semiconductor package with signal distribution element

A method for processing a semiconductor wafer is proposed. The method may include reducing a thickness of the semiconductor wafer. A carrier structure is placed on a first side of the semiconductor wafer, e.g. before or after reducing the thickness of the semiconductor wafer. The method further includes providing a support structure on a second side of the semiconductor wafer opposite to the first side, e.g. after reducing the thickness of the semiconductor wafer. Methods for welding a support structure onto a semiconductor wafer are proposed. Further, semiconductor composite structures with support structures welded onto a semiconductor wafer are proposed.

Method for processing a semiconductor wafer, semiconductor composite structure and support structure for semiconductor wafer

A method of manufacturing a device in a semiconductor body includes forming a first field stop zone portion of a first conductivity type and a drift zone of the first conductivity type on the first field stop zone portion. An average doping concentration of the drift zone is smaller than 80% of that of the first field stop zone portion. The semiconductor body is processed at a first surface and thinned by removing material from a second surface. A second field stop zone portion of the first conductivity type is formed by implanting protons at one or more energies through the second surface. A deepest end-of-range peak of the protons is set in the first field stop zone portion at a vertical distance to a transition between the drift zone and first field stop zone portion in a range from 3 &#x3bc;m to 60 &#x3bc;m. The semiconductor body is annealed.

Method of manufacturing a semiconductor device comprising first and second field stop zone portions

Semiconductor device is provided with a semiconductor body that includes a clamping structure including a first pn junction diode and a second pn junction diode serially connected back to back between a first contact and a second contact. A breakdown voltage of the first pn junction diode is greater than 100 V, and a breakdown voltage of the second pn junction diode is greater than 10 V.

Semiconductor device comprising a clamping structure

A superjunction bipolar transistor includes an active transistor cell area that includes active transistor cells electrically connected to a first load electrode at a front side of a semiconductor body. A superjunction area overlaps the active transistor cell area and includes a low-resistive region and a reservoir region outside of the low-resistive region. The low-resistive region includes a first superjunction structure with a first vertical extension with respect to a first surface at the front side of the semiconductor body. The reservoir region includes no superjunction structure such that the reservoir region includes the semiconductor body that extends from a region located at the first surface to a drain region.

Bipolar transistor with superjunction structure

A semiconductor device includes a first semiconductor region including a first semiconductor material and a second semiconductor region adjoining the first semiconductor region, the second semiconductor region including a second semiconductor material different from the first semiconductor material. The semiconductor device further includes at least one of a drift zone and a base zone in the first semiconductor region, and at least one type of deep-level dopant in an emitter region of the second semiconductor region. The at least one type of deep-level dopant has a distance to the valence or conduction band of at least 100 meV.

Semiconductor device including at least one type of deep-level dopant

A semiconductor device includes a common doping region located within a semiconductor substrate of the semiconductor device. The common doping region includes a first portion. A maximal doping concentration within the first portion is higher than 1&#xb7;10cm. The common doping region includes a second portion. A minimal doping concentration within the second portion is lower than 50% of the maximal doping concentration within the first portion of the common doping region. The common doping region includes a third portion. A minimal doping concentration within the third portion is more than 30% higher than the minimal doping concentration within the second portion. The second portion of the common doping region is located vertically between the first portion of the common doping region and the third portion of the common doping region.

Semiconductor device and method for forming a semiconductor device

A vertical semiconductor device comprises a substrate having a front surface and a back surface, an active area (AA) located in the substrate, having a drift region doped with a first dopant type, an edge termination region (ER) laterally surrounding the active area (AA), a channelstopper terminal provided at the front surface and located in the edge termination region (ER), and a first suppression trench located on a side of the channelstopper terminal towards the active region (AA), and provided adjacent to the channelstopper terminal. Further, a production method for such a semiconductor device is provided.

Semiconductor device with channelstopper and method for producing the same

Semiconductor device with a semiconductor body that includes a clamping structure including a pn junction diode and a Schottky junction diode serially connected back to back between a first contact and a second contact. A breakdown voltage of the pn junction diode is greater than 100 V and a breakdown voltage of the Schottky junction diode is greater than 10 V.

An example power device includes a semiconductor chip and an arrester element configurable to, in response to a voltage across the arrester element being greater than a threshold voltage, create a current path around an isolation layer configured to electrically isolate the semiconductor chip from a heat sink configured to dissipate heat generated by the semiconductor chip. In this example power device, the threshold voltage is less than a breakdown voltage of the isolation layer.

Power device with overvoltage arrester

A superjunction bipolar transistor includes an active transistor cell area that includes active transistor cells electrically connected to a first load electrode at a front side of a semiconductor body. A superjunction area overlaps the active transistor cell area and includes a low-resistive region and a reservoir region outside of the low-resistive region. The low-resistive region includes a first superjunction structure with a first vertical extension with respect to a first surface of the semiconductor body. The reservoir region includes no superjunction structure or a second superjunction structure with a mean second vertical extension smaller than the first vertical extension.

Growing community of inventors

Munich, Germany

Stephan Voss