Infineon Technologies Ag

Stephan Schröder

Manfred Pröll

Herbert Benzinger

Jörg Kliewer

Joerg Vollrath

Ralf Schneider

Georg Erhard Eggers

Koen Van Der Zanden

Aurel Von Campenhausen

Thomas Huber

Arndt Gruber

Tobias Hartner

Evangelos Stavrou

Jürgen Auge

Johann Pfeiffer

Christian Stocken

Claus Engelhardt

Wolfgang Helfer

Heinz-Joachim Neubauer

Semiconductor memories () have segmented word lines (), which in each case have a main word line () made of a conductive metal and a plurality of interconnect segments () coupled to the main word line (), which are coupled to the respective main word line () in each case via at least one contact hole filling (). If one of the contact hole fillings () is defective or at high resistance then functional errors of the semiconductor memory occur. The interconnect segments () of two respective word lines () can be short-circuited in pairs with the aid of switching units (), whereby a static current (I) that flows via the contact hole fillings () can be used for electrically stressing the contact hole fillings (). Electrical stressing of contact hole fillings of segmented word lines is thus made possible.

Integrated semiconductor memory and method for electrically stressing an integrated semiconductor memory

An integrated semiconductor memory device includes at least one memory cell, at least one sense amplifier and a pair of bit lines connected to each sense amplifier, where each memory cell includes a selection transistor and a storage capacitor. The storage capacitor of each memory cell includes a first capacitor electrode and a second capacitor electrode, and the selection transistor of each memory cell includes a first source/drain region that is connected by a first contact connection to one bit line of a pair of bit lines corresponding with the memory cell, and a second source/drain region that is conductively connected to the first capacitor electrode of the storage capacitor of the memory cell. The second capacitor electrode of the storage capacitor of each memory cell is connected to the other bit line of the pair of bit lines corresponding with the memory cell.

Integrated semiconductor memory and method for operating a semiconductor memory

An integrated semiconductor memory includes word lines connected to a first voltage potential via a respective first controllable switch and a respective third controllable switch and to a second voltage potential via a respective second controllable switch. In order to test whether one of the word lines is connected to the first voltage potential via its respective first and third controllable switches, the one of the word lines is connected to a comparator circuit via the respective second controllable switch and a driver line. After the respective first and third controllable switches have been controlled into the on state, in a test operating state of the integrated semiconductor memory, the respective second controllable switch is controlled into the on state and a potential state on the word line is evaluated by the comparator circuit. The result of the evaluation is fed to an external data terminal by an evaluation signal.

Integrated semiconduct memory with test circuit

An integrated circuit, in particular, an integrated memory, contains a control circuit for ascertaining an operating state of the circuit. A self-repair circuit, which is connected to the control circuit, is used to implement self-test and self-repair operation for checking the functioning of, and repairing, defective circuit sections of the integrated circuit. After a supply voltage has been applied to the integrated circuit, the control circuit ascertains an operating state of the integrated circuit and, in a manner dependent thereon, the self-repair circuit is activated by the control circuit in a self-controlling manner in order to put the integrated circuit into a self-repair mode for implementing self-test and self-repair operation. The integrated circuit can be tested for its functionality and repaired even after being soldered onto a module substrate.

Integrated circuit, in particular integrated memory, and methods for operating an integrated circuit

An integrated semiconductor memory including memory cells which can be driven via first and second word lines and can be replaced by redundant memory cells. In the first memory cell type, data can be stored corresponding to the data present at a data input terminal. In the memory cells of a second memory cell type, data can be stored inverted with respect to data present at the data input terminal. The integrated semiconductor memory includes a circuit for data inversion, wherein the data are written to a redundant memory cell, inverted with respect to the data present at the data input terminal if the defective memory cell and the redundant memory cell replacing it are situated in different word line strips of a bit line twist, and if the defective memory cell and the redundant memory cell replacing it are associated with different memory cell types.

Integrated semiconductor memory with redundant memory cells replaceable for either true or complementary defective memory cells

In an arrangement for determining a temperature loading during a soldering process, a semiconductor chip () comprises at least one contact () to be soldered or is electrically conductively connected to at least one contact () to be soldered that is situated outside the semiconductor chip. The semiconductor chip () furthermore comprises a temperature sensor device (), which determines a measurement quantity corresponding to the temperature. A processing device () has an analog-to-digital converter (), which is electrically conductively connected to the temperature sensor device () and converts the measurement quantity into at least one storable signal that represents the temperature loading. A voltage supply device (), which is electrically conductively connected to the temperature sensor device () and the processing device (), supplies these components with an operating voltage. A data memory () serves for storing the at least one storable signal. An electrical line () connected to the data memory () serves for outputting the stored signal. As a result, it is possible to monitor temperature loadings of the semiconductor chip also outside the sphere of influence of the semiconductor manufacturer.

Arrangement for determining a temperature loading of an integrated circuit and method

An integrated circuit includes an input terminal (IN) for application of a supply voltage (Vext) and an output terminal (A) for generation of an output voltage (Vout). A first branch including a first controllable resistance (T) and a second branch including a charge pump () and a second controllable resistance (T) are connected between the input terminal (IN) and the output terminal (A). A control circuit () alters the resistance values of the first and second controllable resistances (T, T) in a manner dependent on a ratio of an actual value (Vout) of the output voltage to a desired value (VSout) of the output voltage and a ratio of an actual value (Vext) of the supply voltage to a desired value (VSext) of the supply voltage. As a result, the output voltage (Vout) can be stabilized to the desired value (VSout) virtually independently of fluctuations of the supply voltage.

Integrated circuit for stabilizing a voltage

An integrated memory has individually addressable normal and redundant units of memory cells. A memory unit is used to store, in a normal mode, an address for one of the normal units which needs to be replaced by one of the redundant units. A comparison unit compares an address which is present on an address bus with an address stored in the memory unit and activates one of the redundant units in the event of a match being identified. The memory also has a test circuit which can be activated by a test mode signal, can reset the memory unit to an initial state, and can store an address for one of the redundant units in the memory unit for subsequently writing an identification code to this redundant unit.

Integrated memory having redundant units of memory cells and method for testing an integrated memory

An integrated semiconductor memory includes at least one word line and a number of memory cells. Each memory cell has a selection transistor coupled to the word line. A word line driver is coupled to the word line. The word line driver provides a first electrical potential or a second electrical potential to the word line such that the word line is activated by the first electrical potential and is deactivated by the second electrical potential. A passive component (e.g., a diode or a resistor) is coupled between the word line and the second electrical potential such that the word line is coupled to the second electrical potential in a high-resistance fashion through the passive component. The passive component is transmissive for a leakage current between the word line and the contact connection.

Integrated semiconductor memory comprising at least one word line and comprising a multiplicity of memory cells

An integrated semiconductor memory device includes a memory cell array (B) with a first bit line and a second bit line (BL, /BL), a controllable resistor (SW) and a control unit () configured to control the controllable resistor. In a first operating state of the integrated semiconductor memory device, the first and second bit lines are connected to one another via a first controllable switch (ET) and also via the controllable resistor (SW) which has been set to a low resistance, to a connection (A) that applies a mid-voltage (V), where the voltage level of the mid-voltage is in the form of an arithmetic mean between a first and second voltage potential (VBLH, VBLL). By virtue of the control unit briefly setting the controllable resistor to a very low resistance in the first operating state of the integrated semiconductor memory device, the period of time required for the first and second bit lines require to assume the mid-voltage (V) is shortened. The influence of capacitive coupling influences, which slow down the charging of the first and second bit lines to the mid-voltage, is significantly reduced as a result.

Integrated semiconductor memory device and method for operating an integrated semiconductor memory device

A circuit for controlling an access to an integrated memory includes a command decoder for receiving at least one external command for an access to the memory. An access controller is connected to the command decoder for receiving internal command signals, which are output by the command decoder. In the course of a memory access, the command decoder outputs a precharge command signal for precharging a row of the memory cell array of the integrated memory. A control circuit, which can determine a temperature of the memory, is designed to temporally variably influence the transmission of the precharge command signal of the command decoder to the access controller in a manner dependent on the temperature of the memory. The write recovery time tWR can be retained even for higher operating frequencies of the memory.

Circuit and method for controlling an access to an integrated memory

A method for repairing an integrated memory having first units of memory cells and second, redundant units of memory cells for replacing first units of memory cells. The first units of memory cells are tested with regard to their functionality. In the case of a defect ascertained in one of the first units, a number of redundant units is programmed as an associated cluster for replacing one or more of the first units. In this way, a repair element is formed with a cluster size corresponding to the number of redundant units. The cluster size of respective repair elements is set in a variable manner by a redundancy circuit. As a result, in a test and repair operation, a comparatively short test time of the memory is made possible in conjunction with a yield that remains good.

Integrated memory and method of repairing an integrated memory

An integrated circuit includes a programming circuit () for generating programming signals (PS, . . . , PS) with a first input terminal (E) for applying a control voltage (ES), a second input terminal (E) for applying a reference voltage (Vref), a storage circuit () with programmable switches () and output terminals (A, . . . , A). The programming circuit in each case generates a programming signal (PS, . . . , PS) when the control voltage (ES) exceeds a predefined threshold voltage formed from the reference voltage. The number of programming signals (PS, . . . , PS) is dependent on the magnitude of the threshold voltage exceeded by the control voltage (ES). The programming signals are used for programming the programmable switches (). The programming state of the programmable switches can be read out via the output terminals (A, . . . , A) of the integrated circuit. The integrated circuit enables the storage of external operating parameters of the integrated circuit.

Integrated circuit for storing operating parameters

A device for cooling memory modules can include a plurality of elements. The elements can thermal couple at least two memory modules. The device can further include a body or a plurality of contact areas bearing in a planar manner.

Device for cooling memory modules

A circuit arrangement for setting a voltage supply for a read/write amplifier of an integrated memory has a first voltage generator circuit for generating a supply voltage for application to the read/write amplifier during an assessment and amplification operation and a second voltage generator circuit for generating a precharge voltage for precharging bit lines of the memory which are connected to the read/write amplifier. A temperature detector circuit, which is connected to the first voltage generator circuit, is used to detect a temperature of the memory and interacts with the first voltage generator circuit to set the supply voltage applied to the read/write amplifier in a manner depending on a temperature of the memory.

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Munich, Germany

Stephan Schröder