Infineon Technologies Ag

Flexenable Limited

Qimonda Ag

Plastic Logic Limited

Infineon Technologies Flash Gmbh & Co. Kg

Spansion Israel Ltd

Stephan Riedel

Roman Knoefler

Stefano Parascandola

Elard Stein Von Kamienski

Boon Hean Pui

David Gammie

Boaz Eitan

Franz Hofmann

Georg Tempel

Michael Specht

Dirk Manger

Matthias Strassburg

Dominik Olligs

Jan Jongman

Veronika Polei

Tiziano Agostinelli

Dirk Caspary

Torsten Mueller

Norbert Schulze

Jeremy Hills

Jens Dienelt

Florian Beug

Anja Wellner

Roland Haberkern

Karsten Neumann

A technique comprising: providing a stack of layers defining at least (a) source and drain electrodes, (b) gate electrode, and (c) semiconductor channel of at least one transistor; depositing one or more organic insulating layers over the stack; removing at least part of the stack in one or more selected regions by an ablation technique; depositing conductor material over the stack in at least the one or more ablated regions and one or more border regions immediately surrounding a respective ablated region; and depositing inorganic insulating material over the stack at least in the ablated regions and the border regions to cover the ablated regions and make direct contact with said conductor material in said one or more border regions all around the respective ablated region.

Protecting transistor elements against degrading species

A device comprising an array of transistors, wherein the device comprises: a first conductor layer at a first level defining a plurality of first conductors providing either source or gate electrodes for said array of transistors; a second conductor layer at a second level defining a plurality of second conductors providing the other of source or gate electrodes for said array of transistors; wherein said second conductor layer further defines routing conductors at one or more locations between said second conductors, each routing conductor connected by one or more interlayer conductive connections to a respective first conductor.

Transistor array routing

A method of operating a device comprising: a first conductor layer defining a plurality of source conductors each associated with a respective group of transistors, and a plurality of drain conductors each associated with a respective transistor; a semiconductor layer defining semiconductor channels between said source and drain conductors; a second conductor layer defining a plurality of gate conductors each associated with a respective set of transistors, and one or more storage capacitor conductors capacitively coupled to the drain conductors for a respective set of transistors; the method comprising: using the gate conductors to switch the transistors between on and off states; and using the storage capacitor conductors to reduce the conductivity of one or more semiconductor layer connecting the drain conductor of each transistor in the on state to source and/or drain conductors other than those associated with that transistor.

Reducing parasitic leakages in transistor arrays

We describe a method of reducing artefacts in an image displayed by an active matrix electro-optic display and display driver, the electro-optic display driver comprising a plurality of active matrix pixel drivers each driving a respective pixel of the electro-optic display, each active matrix pixel driver having an associated storage capacitor coupled to a common backplane connection of the display driver, pixels of the electro-optic display having a common pixel electrode, the method comprising: driving the electro-optic display with a null frame during a power-down procedure of the display.

Display systems

A technique of operating a device comprising a patterned conductor layer defining source electrode circuitry and drain electrode circuitry for a plurality of transistors; a semiconductor layer providing a respective semiconductor channel for each transistor between source electrode circuitry and drain electrode circuitry; and gate electrode circuitry overlapping the semiconductor channels of the plurality of transistor devices for switching the semiconductor channels between two or more levels of conductance; wherein the technique comprises using one or more further conductors independent of said gate electrode circuitry to capacitatively induce a reduction in conductivity of said one or more areas of said semiconductor layer outside of said semiconductor channels.

Suppressing leakage currents in a multi-TFT device

A technique for creating a conductive connection between a contact part () of a display back plane () and a common electrode () of a display front plane (), comprising the step of compressing a compressible conductive component () between the display front plane () and the display back plane (), wherein the method further comprises the step of interposing one or more layers () having a low modulus of elasticity not larger than 5 GPa between the contact part () and the compressible conductive component () prior to the compressing step.

Forming a conductive connection between a common electrode of an optical front plane and an electrical contact part of an opposite back plane

A technique comprising: producing a plurality of devices according to a common production process; and determining the thickness of a layer of one of said plurality of devices using an indicator of a first electrical property dependent on the area of overlap between a first element of the device and a second element of the device partially underlying said first element via said layer, wherein the method further comprises: additionally using an indicator of a second electrical property dependent on the area of overlap between said first element of the device and a third element of the device also partially underlying said first element via said layer, wherein (a) the difference between (i) a measured indicator of said first electrical property, and (ii) a measured indicator of said second electrical property provides a more reliable indicator of the thickness of said layer than (b) an indicator of said first electrical property.

Determining layer thickness

The present invention is a method, circuit and system for erasing a non-volatile memory cell. A shunting element (e.g. transistor) may be introduced and/or activated between bit-lines to which one or more NVM cells being erased are connected. The shunting element may be located and/or activated across two bit-lines defining a given column of cells, where one or a subset of cells from the column may be undergoing an erase operation or procedure. The shunting element may be located, and/or activated, at some distance from the two bit-lines defining the given column of cells, and the shunting element may be electrically connected to the bit-lines defining the column through select transistors and/or through global bit-lines.

Method and circuit for erasing a non-volatile memory cell

In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory cell contacting region. The fin structure may include a memory cell region having a plurality of memory cell structures being disposed above one another, each memory cell structure having an active region of a respective memory cell. Furthermore, the memory cell contacting region may be configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region may include a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to the main processing surface of the substrate.

Integrated circuits having a contact region and methods for manufacturing the same

The bit lines are produced by an implantation of a dopant by means of a sacrificial hard mask layer, which is later replaced with the gate electrodes formed of polysilicon in the memory cell array. Striplike areas of the memory cell array, which run transversely to the bit lines, are reserved by a blocking layer to be occupied by the bit line contacts. In these areas, the hard mask is used to form contact holes, which are self-aligned with the implanted buried bit lines. Between the blocked areas, the word lines are arranged normally to the bit lines.

Semiconductor memory device and method of production

A memory layer sequence comprising a lower confinement layer (), a charge-trapping layer (), and an upper confinement layer () is applied on the main surface of a silicon substrate (). By a photolithography step, trenches running parallel at a distance from one another are etched to delimitate the active area. A trench filling () is applied by growth or deposition of dielectric material or by a selective oxidation of the substrate material. After the removal of the charge-trapping layer sequence in a peripheral area and the deposition of a gate dielectric material provided for the transistors of an addressing circuitry, wordline stacks () are formed.

Method for producing charge-trapping memory cell arrays

Insulation regions in the manner of STI isolations, which run transversely with respect to the word lines, isolate the source/drain regions of adjacent memory cells. Metallic bit lines are applied on the top side and patterned for example along zigzag lines such that the source/drain regions of a memory transistor which are contact-connected by the bit lines are in each case electrically connected by two mutually adjacent bit lines.

Semiconductor memory with virtual ground architecture

A semiconductor device comprises a memory cell () including a transistor body () having a top surface () and including a first doping area () and a second doping area () with a channel region () in between. The memory cell () further includes a gate electrode () arranged above the channel region () and separated therefrom by a dielectric layer (). An oxide-nitride-oxide layer () has first portions () and second portions (). The first portions () of the oxide-nitride-oxide layer () are arranged above at least parts of the first and second doping areas () and are substantially parallel to the top surface () of the transistor body (). The second portions () of the oxide-nitride-oxide layer () are adjacent to the gate electrode () and extend in a direction not substantially parallel to the top surface () of the transistor body ().

Semiconductor device and method of producing a semiconductor device

A non-volatile semiconductor memory includes a substrate having a substrate region, at least one word line, a plurality of non-volatile memory cells arranged in a plurality of sectors and further comprising first wells of a first doping type, electrically insulating elements and switching elements. Each sector includes a plurality of non-volatile memory cells commonly arranged in a respective first well. The at least one word line electrically connecting memory cells of a group of sectors among the plurality of sectors. The first wells are separated from the substrate region and from each other by means of the electrically insulating elements. Each first well is connected to a respective switching element and the semiconductor memory is constructed such that each first well is biasable to a predetermined potential by means of the respective switching element. Further, a method is provided for operating the above non-volatile semiconductor memory.

Non-volatile semiconductor memory

The method aims at improving the charge confinement of the memory layer at the edges facing the regions of buried bitlines. After the deposition of the memory layer between confinement layers and the implantation of dopants for bitlines and source/drain regions, an oxidation of semiconductor material to form upper bitline isolation regions takes place. By this method, additional oxide regions are produced at the edges of the memory layer in the same oxidation step. Either a silicon layer may be deposited and reduced to sidewall spacers, which are subsequently oxidized; or recesses are etched into the memory layer and subsequently filled with semiconductor oxide.

Growing community of inventors

Dresden, Germany

Stephan Riedel