Nxp Usa, Inc.

Freescale Semiconductor,inc.

Nxp B.v.

Bayerische Motoren Werke Aktiengesellschaft

Stephan Matthias Herrmann

Michael Andreas Staudenmaier

Gaurav Gupta

Joachim Fader

Dirk Wendel

Naveen Kumar Jain

Shreya Singh

Robert Cristian Krutsch

Chanpreet Singh

Sharath Subramanya Naidu

Rahul Jain

Sumit Mittal

Ray Charles Marshall

Wilhard Christophorus Von Wendorff

Albrecht Neff

Stefan Singer

Deboleena Sakalley

Norbert Stoeffler

Nitin Singh

Vivek Singh

Amit Jindal

Ajit Singh

Navdeep Singh Gill

Jochen Gerster

Shivali Jain

Leonardo Surico

Michael Deur

Snehlata Gutgutia

Nikhil Sharma

Pranshu Agrawal

Ritesh Agrawal

Navarshi Dhiman

Maninder Kumar

Bhagwan Babu Jha

Aman Arora

Jeetendra Kumar Gupta

A system, method, and apparatus are provided for on-the-fly camera image processing configuring a system-on-chip (SoC) configuration register memory with one or more synchronization settings; processing multiple camera image frame sequences having different specified exposures to detect a set of complete frames from the camera image frame sequences which have a first common frame number; identifying a valid combination of different exposures from the image frame sequences having a second common frame number succeeding the first common frame number; and processing the valid combination of different exposures from the first and second camera image frame sequences to generate output data from the ISP pipeline.

Real time stream camera ISP with loosely coupled control loop

Embodiments provide line-based feature generation for vision-based driver assistance systems and methods. For one embodiment, a feature generator includes a circular buffer and a processor coupled to an image sensor. The circular buffer receives image data from the image sensor and stores N lines at a time of an image frame captured by the image sensor. The N lines of the image frame are less than all of the lines for the image frame. The processor receives the N lines from the circular buffer and stores one or more features generated from the N lines in a memory. Iterative blocks of N lines of image data are processed to complete processing of the full image frame, and multiple frames can be processed. The generated features are analyzed by a vision processor to identify, classify, and track objects for vision-based driver assistance and related vision-based assistance actions.

Line-based feature generation for vision-based driver assistance systems and methods

A system-on-chip (SoC) includes first and second processing circuits and a data exchange circuit such that the first processing circuit is configured to process image lines based on corresponding sets of processing attributes. The first processing circuit is further configured to continuously receive and process the image lines one after the other to generate corresponding output data, and the second processing circuit is configured to continuously receive by way of the data exchange circuit, the generated output data for processing the generated output data. The data exchange circuit is thus configured to control data flow between the first processing circuit and the second processing circuit such that the first processing circuit and the second processing circuit parallelly process corresponding data associated with same or different image lines.

System for parallelly processing image lines from multiple image sensors

A system for processing multiple images includes an access serializer, trigger controllers, a first-in-first-out (FIFO) memory, and an image signal processing (ISP) pipeline circuit. The access serializer serializes access requests that are associated with processing of input image lines of the images. The trigger controllers decode corresponding serialized access requests to generate trigger identifiers (IDs), respectively. The FIFO memory receives a corresponding trigger ID from each trigger controller and provides the trigger IDs to the ISP pipeline circuit based on an order of reception of the trigger IDs. The ISP pipeline circuit receives the input image lines associated with the trigger IDs, and based on a corresponding set of configuration parameters associated with the input image lines, processes the input image lines in an order of reception of the trigger IDs, to generate processed image lines, respectively.

System for processing images from multiple image sensors

A video device is described that includes: a host processor comprising at least one input video port configured to receive a plurality of video data signals that comprise video data and embedded data from a plurality of virtual channels in a received frame; and a memory operably coupled to the host processor and configured to receive and store video data. The host processor is configured to segregate the video data from the embedded data in the received frame and process the embedded data individually.

Video device and method for embedded data capture on a virtual channel

A processing engine for classifying data according to a decision tree having n-nodes is disclosed, wherein each node is represented by a respective test according to which a flag may be set or unset, comprising: a respective test unit and corresponding to each node, having an output flag and being configured to set or unset the respective output flag according to an output of the respective test; a memory configured to hold an n-bit word, each bit corresponding to a one of the respective output flags; and a data-structure configured as a look up table, each entry of the look up table representing a class of the data. Corresponding methods are also disclosed, as are devices and systems incorporating such processing engines.

Methods, processing engines, and microprocessors for classifying data according to decision trees

An electronic device is described that includes: a host processor comprising at least one input port configured to receive a plurality of data signals on a plurality of virtual channels; and a memory operably coupled to the host processor and configured to receive and store data. The host processor is configured to enable and disable individual virtual channels from the plurality of virtual channels and is configured to only store data in memory associated with enabled virtual channels, and discard data from disabled channels.

Electronic device and method for coherent enable/disable on a virtual data channel

Methods and systems are disclosed for asymmetric memory access to memory banks within integrated circuit (IC) systems. Disclosed embodiments include a memory and a memory controller within an integrated circuit. The memory includes a number of different memory banks, and the memory controller includes a number of different access ports coupled to the memory banks. The memory controller is also configured to provide asymmetric memory access for access requests to memory banks based upon access ports used for memory access requests. Additional disclosed embodiments further use asymmetric access times or asymmetric access bandwidths to provide this asymmetric access to memory banks within system memories for integrated circuit (IC) systems. By providing asymmetric access times or bandwidths for multiple access ports within a memory controller to multiple different memory banks within a system memory, overall access latency or system cost is reduced for the IC systems.

Systems and methods for asymmetric memory access to memory banks within integrated circuit systems

A method of performing compression of image data for at least one image is described. The method comprises receiving image data of at least a part of the at least one image, encoding the received image data into at least one compressed data block, applying at least one bandwidth limit to the at least one compressed data block, and outputting the at least one bandwidth limited compressed data block to a buffer. The method further comprises dynamically updating the at least one bandwidth limit applied to the at least one compressed data block base at least partly on a fill level of the buffer.

Method and apparatus for performing compression of image data

A method and apparatus are provided for controlling data flow by storing variable length encoded information bits in a circular buffer in a write operation to a virtual write address comprising a first wrap bit value appended by a current write address within the buffer address range and generating an interrupt alarm if the virtual write address crosses a virtual alarm address comprising a second wrap bit value appended by an alarm address within the buffer address range, where the first and second wrap bit values each toggle between first and second values every time the current write address or alarm address, respectively, wraps around the circular buffer, thereby synchronizing data flow in the circular buffer and/or preventing buffer overflow.

Shared buffer management for variable length encoded data

A device has a cache memory for temporarily storing contents of a buffer memory. The device has a mirror unit coupled between the cache memory and the buffer memory. The mirror unit is arranged for providing at least two buffer mirrors at respective different buffer mirror address ranges in the main address range by adapting the memory addressing. Due to the virtual mirrors data on a respective address in any of the respective different buffer mirror address ranges is the data of the buffer memory at a corresponding address in the buffer address range. The device enables processing of a subsequent set of data in the buffer memory via the cache memory without invalidating the cache by switching to a different buffer mirror.

Device having a cache memory

A method for detecting a freeze-frame condition comprises receiving a sequence of images from at least one digital device; selectively encoding a first subset of the sequence of images using a first coding scheme that causes an adjustment to an image characteristic of the selected images being encoded; selectively encoding a second subset of the sequence of images using a second coding scheme; storing the first encoded subset and second encoded subset; retrieving the stored first encoded subset and second encoded subset; selectively decoding the first subset of the selected images using the first coding scheme and selectively decoding the second subset of the selected images using the second coding scheme to re-create the sequence of images. A freeze-frame condition in the re-created sequence of images is identifiable based on a plurality of decoded images being different with respect to the image characteristic across multiple decoded image frames.

Method and video system for freeze-frame detection

A data logging system for logging input data received from a data source is described. The data logging system has a data storage memory. A data input is arranged to repeatedly receive input data having a temporal input data resolution. A write controller is arranged to write newly received input data as received via the data input into the data storage memory. The writing comprises writing the newly received input data at the temporal input data resolution. The writing comprises keeping recent data at the temporal input data resolution in the data storage memory, and overwriting part of old data with newly received input data while keeping another part of the old data in the data storage memory at lower data resolution.

Data logging system and method

A memory controller that implements an interleaving and arbitration scheme includes an address decoder that selects a memory bank for an access request based on a set of address least significant bits included in the access request. A core requiring sequential access to memory is routed to consecutive memory banks of the memory for consecutive access requests. When multiple cores request access to the same memory bank, an arbiter determines an access sequence for the cores. The arbiter can modify the access sequence without significantly increasing the complexity of the memory controller. The address decoder determines whether the selected memory banks are available and also whether an access request is a wide access request, in which case it selects two consecutive memory banks.

Memory controller with interleaving and arbitration scheme

A video processing device for generating an output video stream on the basis of two or more concurrent input video streams and a method thereof are described. Each input video stream comprises a sequence of input images. The output video stream comprises a sequence of output images. The video processing device generates each output image by merging a respective set of input images. The set of input images comprises one input image from each input video stream. The video processing device merges the input images in a series of merging rounds. Each merging round comprises forming an output tile by merging a set of input tiles, and writing the output tile to an output memory unit. The set of input tiles comprises one input tile from each input image of the respective set of input images. The output tiles written to the output memory unit represent the output image.

Growing community of inventors

Markt Schwaben, Germany

Stephan Matthias Herrmann