Intel Corporation

Intel Mobile Communications Gmbh

Intel Deutschland Gmbh

Stephan Leuschner

Uwe Hodel

Marko Radosavljevic

Han Wui Then

Sansaptak W Dasgupta

Harald Gossner

Peter Baumgartner

Domagoj Siprak

Richard Geiger

Jan-Erik Mueller

Peter Pfann

José Moreira

Chuanzhao Yu

David A Newman

Gerhard Knoblinger

Michael Fulde

Florian Mrugalla

Daniel Sira

Michael Wagner

Jose Pedro Diogo Faisca Moreira

Amr Zohny

A variable capacitance III-N device having multiple two-dimensional electron gas (2DEG) layers are described. In some embodiments, the device comprises a first source and a first drain; a first polarization layer adjacent to the first source and the first drain; a first channel layer coupled to the first source and the first drain and adjacent to the first polarization layer, the first channel layer comprising a first 2DEG region; a second source and a second drain; a second polarization layer adjacent to the second source and the second drain; and a second channel layer coupled to the second source and the second drain and adjacent to the second polarization layer, the second channel layer comprising a second 2DEG region, wherein the second channel layer is over the first polarization layer.

Variable capacitance device with multiple two-dimensional electron gas (2DEG) layers

Techniques are provided for fanning out a signal from a balun. In various aspects, the system can include a balun configured to receive a signal for transmission at an input and to provide a representation of the signal at an output, a plurality of pass gate circuits, each pass gate circuit configured to receive the representation of the signal at a first node, to receive a control signal at a second node to pass the representation of the signal to a third node when the control signal is in a first state, and to isolate the representation of the signal from the third node when the control signal is in a second state. The first state of the control signal can include a non-zero voltage, and the second state of the control signal can include the non-zero voltage with a polarity opposite the non-zero voltage of the first state.

Techniques for multiple signal fan-out

Gallium nitride (GaN) transistors with source and drain field plates are described. In an example, a transistor includes a gallium nitride (GaN) layer above a substrate, a gate structure over the GaN layer, a source region on a first side of the gate structure, a drain region on a second side of the gate structure, the second side opposite the first side, a source field plate above the source region, and a drain field plate above the drain region.

Gallium nitride transistors with source and drain field plates and their methods of fabrication

A Group III-Nitride (III-N) device structure is provided which comprises: a heterostructure having three or more layers comprising III-N material, an anode within a recess that extends through two or more of the layers, wherein the anode is in electrical contact with the first layer, a cathode comprising donor dopants, wherein the cathode is on the first layer of the heterostructure; and a conducting region in the first layer in direct contact to the cathode and conductively connected to the anode. Other embodiments are also disclosed and claimed.

Group III-nitride Schottky diode

A Group III-Nitride (III-N) device structure is provided comprising: a heterostructure having three or more layers comprising III-N material, an anode n+ region and a cathode comprising donor dopants, wherein the anode n+ region and the cathode are on the first layer of the heterostructure and wherein the anode n+ region and the cathode extend beyond the heterostructure, and an anode metal region within a recess that extends through two or more of the layers, wherein the anode metal region is in electrical contact with the first layer, wherein the anode metal region comprises a first width within the recess and a second width beyond the recess, and wherein the anode metal region is coupled with the anode n+ region. Other embodiments are also disclosed and claimed.

Group III-nitride silicon controlled rectifier

A Group III-Nitride (III-N) device structure is presented comprising: a heterostructure having three or more layers comprising III-N material, a cathode comprising donor dopants, wherein the cathode is on a first layer of the heterostructure, an anode within a recess that extends through two or more of the layers of the heterostructure, wherein the anode comprises a first region wherein the anode is separated from the heterostructure by a high k dielectric material, and a second region wherein the anode is in direct contact with the heterostructure, and a conducting region in the first layer in direct contact to the cathode and conductively connected to the anode. Other embodiments are also disclosed and claimed.

Group III-nitride antenna diode

Examples provide a wideband filter structure and apparatus, a radio transceiver, a mobile terminal, and a method for filtering a radio signal. The wideband filter structure () for a radio signal comprises a combination of at least one acoustic resonator () and at least one analog resonator (). The acoustic resonator () is coupled to the analog resonator (). The wideband filter structure () comprises a further component (), which is coupled to the combination of the acoustic resonator () and the analog resonator ().

Wideband filter structure and apparatus, radio transceiver, mobile terminal, method for filtering a radio signal

An apparatus for reducing a magnetic coupling between a first electronic circuit and a second electronic circuit is provided. The apparatus includes a conductor loop enclosing the first electronic circuit or the second electronic circuit, and a tuning element coupled to the conductor loop. The conductor loop and the tuning element form a resonant circuit, wherein the tuning element is configured to adjust a resonance frequency of the resonant circuit to a frequency related to a frequency of a signal processed by the second electronic circuit.

Apparatus for reducing a magnetic coupling between a first electronic circuit and a second electronic circuit

A communication matching network for multi-harmonic suppression includes a communication circuit configured to provide a signal. The communication matching network further includes a matching circuit configured to receive the signal from the communication circuit and suppress one or more harmonics of the received signal to generate a filtered signal, wherein the matching circuit includes a transformer comprising a first winding and a second winding, wherein the first winding includes a first inductance and the second winding includes a second inductance and wherein the matching network includes a harmonic trap including a third inductance such that the third inductance is located inside or within a physical layout of the first winding and/or the second winding. The communication matching network further includes a receiver circuit configured to receive the filtered signal from the matching circuit for further processing.

Multi-harmonic matching networks

A transformer is provided. The transformer includes at least one first primary turn; at least one second primary turn; and a first secondary turn and a second secondary turn. The first secondary turn and the second secondary turn are arranged laterally between the at least one first primary turn and the at least one second primary turn. The first secondary turn and the second secondary turn are arranged one above the other.

Transformer and electrical circuit

A differential amplifier stage may include: a first transistor having a gate terminal; a second transistor having a gate terminal; and a voltage limiting circuit coupled to the gate terminals of the first and second transistors, wherein the voltage limiting circuit limits a gate voltage supplied to at least one of the gate terminals of the first and second transistors.

Amplifier stage

A digital-to-analog converter circuit including a plurality of digital-to-analog converter cells is provided. A first digital-to-analog converter cell of the plurality of digital-to-analog converter cells includes a cell control module configured to provide alternatingly a first voltage and a second voltage to a first electrode of a capacitive element of the first digital-to-analog converter cell based on a digital input signal during a predefined time interval. A second digital-to-analog converter cell of the plurality of digital-to-analog converter cells includes a cell control module configured to provide a third voltage to a first electrode of a capacitive element of the second digital-to-analog converter cell during the predefined time interval. The first voltage is higher than an upper threshold voltage corresponding to a first digital threshold level of the digital input signal and the second voltage is lower than a lower threshold voltage corresponding to a second digital threshold level of the digital input signal. The third voltage is constantly between the upper threshold voltage and the lower threshold voltage.

Digital-to-analog converter circuit, an apparatus for providing a radio frequency transmit signal and a method of digital-to-analog conversion

A transmission arrangement is disclosed having an amplifier which is set up to amplify a transmission signal and to provide it as an amplified transmission signal in differential form, an analysis circuit for determining a property of the amplified transmission signal, and a differential feedback path which is set up to supply the amplified transmission signal to the analysis circuit in differential form.

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Munich, Germany

Stephan Leuschner