Infineon Technologies Ag

Other

International Business Machines Corporation

Infineon Technologies North America Corp.

Qimonda Ag

Siemens Aktiengesellschaft

Stephan Kudelka

Helmut Horst Tews

Alexander Michaelis

Uwe Schroeder

Uwe Paul Schroeder

Jack Allan Mandelman

Irene Lennox McStay

Jochen C Beintner

Ulrike Gruening

Thomas Hecht

Carl John Radens

Harald Seidl

Martin Popp

Stefan Jakschik

Stephen Rahn

Ramachandra Divakaruni

Thomas W Dyer

Rajarao Jammy

Albert Birner

Rama Divakaruni

Martin Gutsche

Wolfgang Bergner

Kenneth T Settlemyer, Jr

Mary Elizabeth Weybright

Brian S Lee

Oliver Genz

Lars Heineck

Jörn Lützen

Raj Jammy

David Rath

Jeffrey P Gambino

Oleg Gluschenkov

Michael Patrick Chudzik

Rolf Weis

Till Schloesser

Gary Bela Bronner

Johnathan E Faltermeier

Matthias Goldbach

Larry Alan Nesbit

Hans-Peter Moll

Dirk Manger

Michael Lester Wise

Andreas Knorr

Peter Moll

Till Schlösser

Thomas S Rupp

Franz X Zach

Albrecht Kieslich

Kristin Schupke

Uwe Schröder

Bernd Hintze

Elke Erben

Annette Saenger

Odo Wunnicke

Annette Sänger

Tim Boescke

Kil-Ho Lee

Andreas Orth

Johannes Heitmann

Matthias Schmeide

Christian Kapteyn

Joerg Schumann

Guenther Aichmayr

Daniel Koehler

Linda A Chen

Alexander Michaeli

Suri Hegde

Lars Oberbeck

Jonas Sundqvist

Kevin Pears

Ramac Divakaruni

Johann Steinmetz

Gerd Fehlauer

Venkatachaiam C Jaiprakash

The present invention relates to a method for depositing a dielectric material comprising a transition metal compound. After providing a substrate, a first pre-cursor comprising a transition metal compound and a second pre-cursor predominantly comprising at least one of water vapour, ammonia and hydrazine are successively applied on the substrate for forming a first layer of transition metal containing material. In a next step the first pre-cursor and a third pre-cursor comprising at least one of ozone and oxygen are successively applied on the first layer for forming a second layer of the transition metal containing material.

Deposition method for a transition-metal-containing dielectric

In a method for producing a conductive layer a substrate is provided. On the substrate, a layer includes at least two different metal nitrides. In one embodiment, on a surface of the substrate a first metal nitride layer is deposited, followed by a second metal nitride layer formed thereon. A third metal layer is then deposited on a surface of the second metal nitride layer.

Method of producing a conductive layer including two metal nitrides

A method produces stacked capacitors for dynamic memory cells, in which a number of trenches () are formed in the masking layer (), each trench () being arranged above a respective contact plug () and extending from the top () of the masking layer () to the contact plugs (). A conductive layer () covers the side walls () of the trenches () and the contact plugs () in order to form a first electrode () of a stacked capacitor (). In an upper region (), which is remote from the contact stack (), the conductive layer () is replaced by an insulating layer, so that it is not possible for a short circuit to arise in the event of any adhesion between adjacent electrodes.

Stacked capacitor and method for producing stacked capacitors for dynamic memory cells

The present invention relates to a method of fabricating a capacitor in a semiconductor substrate. The capacitor is fabricated such that the capacitor comprises: a trench inside a substrate, the trench having a lower region and an upper region, wherein the trench's diameters in the lower region is larger than in the upper region; a first electrode; a dielectric layer on top of the first electrode; a conductive layer on top of the electric layer, the conductive layer forming a second electrode of the capacitor; and a plug forming a closed cavity inside the lower region.

Method for fabricating a capacitor

The present invention relates to a manufacturing method for a trench capacitor having an isolation collar which is electrically connected with a substrate on a single side via a buried contact. More specifically, the present invention relates to manufacturing method for a trench capacitor having an isolation collar with a metal conductive fill in the collar region connected to a metal fill in the capacitor region.

Manufacturing method for a trench capacitor having an isolation collar electrically connected with a substrate on a single side via a buried contact for use in a semiconductor memory cell

Fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected thereto on one side through a buried contact, in particular, for a semiconductor memory cell with a planar selection transistor in the substrate and connected through the buried contact, includes providing a trench using an opening in a hard mask, providing a capacitor dielectric in lower and central trench regions, the collar in central and upper trench regions, and a conductive filling at least as far as the insulation collar topside, completely filling the trench with a filling material, carrying out STI trench fabrication process, removing the filling material and sinking the filling to below the collar topside, forming an insulation region on one side above the collar; uncovering a connection region on a different side above the collar, and forming the buried contact by depositing and etching back a metallic filling.

Method for fabricating trench capacitor with insulation collar electrically connected to substrate through buried contact, in particular, for a semiconductor memory cell

A method for fabricating a trench structure, in particular a trench capacitor with an insulation collar, which is electrically connected to a substrate on one side via a buried contact. Fabrication includes, for example, providing a trench in the substrate using a hard mask with a corresponding mask opening; providing an at least partial trench filling; providing a liner on the resulting structure; carrying out an oblique implantation of impurity ions onto the liner for altering the etching properties of an implanted partial region of the liner; selectively removing the implanted partial region of the liner by a first etching for forming a liner mask from the complimentary partial region of the liner, which partially masks the top side of the trench filling; removing a part of the trench filling by a second etching using the liner mask; and replacing the removed part of the trench filling.

Method for fabricating a trench structure which is electrically connected to a substrate on one side via a buried contact

A dielectric barrier layer composed of a metal oxide is applied in thin layers with a thickness of less than 20 nanometers in the course of processing semiconductor devices by sequential gas phase deposition or molecular beam epitaxy in molecular individual layers on differently structured base substrates. The method allows, inter alias, effective conductive diffusion barriers to be formed from a dielectric material, an optimization of the layer thickness of the barrier layer, an increase in the temperature budget for subsequent process steps, and a reduction in the effort for removing the temporary barrier layers.

Barrier layer and a method for suppressing diffusion processes during the production of semiconductor devices

The present invention provides a method for expanding a trench in a semiconductor structure. A trench is provided in a semiconductor substrate, hydrogen-terminated silicon surfaces are provided in the trench, anisotropic wet etching of the silicon surfaces in the trench with an alkaline etchant occur, and the trench is rinsed with a proton-containing neutralizing agent for the removal of the alkaline etchant. Between the wet etching step and the rinsing step, an anodic passivation of the etched silicon surfaces in the trench is carried out, in the course of which an etching stop layer is formed on the etched silicon surfaces in the trench.

Method for expanding a trench in a semiconductor structure

The surface area of the walls of a trench formed in a substrate is increased. A barrier layer is formed on the walls of the trench such that the barrier layer is thinner near the corners of the trench and is thicker between the corners of the trench. A dopant is introduced into the substrate through the barrier layer to form higher doped regions in the substrate near the corners of the trench and lesser doped regions between the corners of the trench. The barrier layer is removed, and the walls of the trench are etched in a manner that etches the lesser doped regions of the substrate at a higher rate than the higher doped regions of the substrate to widen and lengthen the trench and to form rounded corners at the intersections of the walls of the trench.

Selective etching to increase trench surface area

A trench capacitor with improved strap is disclosed. The strap is located above the top surface of the capacitor. The top surface of the trench capacitor, which is formed by the top surfaces of the collar and storage plate, is planar. By locating the strap on a planar surface, the divot present in conventional strap processes is avoided. This results in improved strap reliability and device performance.

Trench capacitor with buried strap

Semiconductor devices having improved isolation are provided along with methods of fabricating such semiconductor devices. The improved isolation includes an encapsulated spacer formed within a gate region of a device.

Method of making encapsulated spacers in vertical pass gate DRAM and damascene logic gates

In a method for forming patterned ceramic layers, a ceramic material is deposited on a substrate and is subsequently densified by heat treatment, for example. In this case, the initially amorphous material is converted into a crystalline or polycrystalline form. In order that the now crystalline material can be removed again from the substrate, imperfections are produced in the ceramic material, for example by ion implantation. As a result, the etching medium can more easily attack the ceramic material, so that the latter can be removed with a higher etching rate. Through inclined implantation, the method can be performed in a self-aligning manner and the ceramic material can be removed on one side, by way of example, in trenches or deep trench capacitors.

Method for patterning ceramic layers

Damage to the rim of a semiconductor wafer caused by etching processes is reduced by forming a rim of photoresist or other material around the outer edge of the wafer that has a thickness such that images projected on the rim are sufficiently out of focus that they do not develop, so that etching takes place only in the interior.

Process to suppress lithography at a wafer edge

A method for fabricating a semiconductor trench structure includes forming a trench in a semiconductor substrate and filling it with a filler. A first thermal process having a first maximum temperature cures the filler. Removing the filler from an upper region of the trench as far as a boundary surface defines a collar region. In a second thermal process having a second maximum temperature that is not significantly higher than the first maximum temperature, a liner is deposited on the collar region and the boundary surface. The liner is removed from the boundary surface, thereby exposing the filler. The filler is then removed from a lower region of the trench.

Semiconductor trench structure

Growing community of inventors

Ottendorf-Okrilla, Germany

Stephan Kudelka