Advanced Micro Devices Corporation

Globalfoundries Inc.

Stephan Kruegel

Karsten Wieczorek

Manfred Horstmann

Klaus Hempel

Sven Beyer

Markus Lenski

Rolf Stephan

Thomas Feudel

Ralf Van Bentum

Ekkehard Pruefer

Gert Burbach

Andreas Ott

Michael Raab

Wolfgang Buchholtz

Falk Graetsch

Roland Stejskal

In a replacement gate approach, a superior cross-sectional shape of the gate opening may be achieved by performing a material erosion process in an intermediate state of removing the placeholder material. Consequently, the remaining portion of the placeholder material may efficiently protect the underlying sensitive materials, such as a high-k dielectric material, when performing the corner rounding process sequence.

Method for making high-K metal gate electrode structures by separate removal of placeholder materials

By modifying the dielectric liner for a spacer structure so as to exhibit an enhanced diffusion blocking characteristic, for instance by incorporating nitrogen, the out-diffusion of P-dopants, such as boron, into the dielectric material may be significantly reduced. Consequently, transistor performance, especially of P-type transistors, may be significantly enhanced while nevertheless a high degree of compatibility with conventional techniques may be maintained.

Drain/source extension structure of a field effect transistor with reduced boron diffusion

Superior fill conditions in a replacement gate approach by corner rounding prior to completely removing a placeholder material

By performing an anisotropic resist modification prior to the actual resist trimming process, the profile of the end portions of the resist features may be significantly enhanced, for instance by providing substantially vertical sidewall portions. Consequently, an overlap of gate electrodes with the respective isolation structures may be obtained, while nevertheless the probability for a short circuit between opposing end portions of the gate electrodes may be significantly reduced, thereby providing the potential for further scaling down device dimensions.

Method of patterning gate electrodes by reducing sidewall angles of a mask layer

By forming a non-oxidizable liner in isolation trenches, the creation of compressive stress may be significantly reduced, wherein, in illustrative embodiments, silicon nitride may be used as liner material. For this purpose, the etch behavior of the silicon nitride may be efficiently modified on the basis of an appropriate surface treatment, thereby providing a high degree of material integrity during a subsequent etch process for removing non-modified portions of silicon nitride, which may also be used as an efficient CMP stop layer.

Trench isolation structure for a semiconductor device with reduced sidewall stress and a method of manufacturing the same

Different types of crystalline semiconductor regions are provided on a single substrate by forming a dielectric region within a first crystalline semiconductor region. Thereafter, a second crystalline region is positioned above the dielectric region by wafer bond techniques. In preferred embodiments, isolation structures may be formed in the first crystalline region along with the dielectric region. In particular, crystalline semiconductor regions of different crystallographic orientations may be formed, wherein a high degree of flexibility and compatibility with currently used CMOS processes is maintained.

Technique for forming a substrate having crystalline semiconductor regions of different characteristics

In a trench isolation structure of a semiconductor device, oxide liners are formed within the trenches, wherein a non-oxidizable mask is employed during various oxidation steps, thereby creating different types of liner oxides and thus different types of corner rounding and thus mechanical stress. Therefore, for a specified type of circuit elements, the characteristics of the corresponding isolation trenches may be tailored to achieve an optimum device performance.

Method of manufacturing a trench isolation structure for a semiconductor device with a different degree of corner rounding

According to one illustrative embodiment of the present invention, a method of forming a field effect transistor includes the formation of a doped high-k dielectric layer above a substrate including a gate electrode formed over an active region and separated therefrom by a gate insulation layer. A heat treatment is carried out with the substrate to diffuse dopants from the high-k dielectric layer into the active region to form extension regions. The high-k dielectric layer is patterned to form sidewall spacers at sidewalls of the gate electrode and an implantation process is carried out with the sidewall spacers as implantation mask to form source and drain regions.

Methods of forming drain/source extension structures of a field effect transistor using a doped high-k dielectric layer

The polysilicon gate electrode of a MOS transistor may be substantially completely converted into a metal silicide without sacrificing the drain and source junctions in that a thickness of the polysilicon layer, for forming the gate electrode, is targeted to be substantially converted into metal silicide in a subsequent silicidation process. The gate electrode, substantially comprised of metal silicide, offers high conductivity even at critical dimensions in the deep sub-micron range, while at the same time the effect of polysilicon gate depletion is significantly reduced. Manufacturing of the MOS transistor, having the substantially fully-converted metal silicide gate electrode, is essentially compatible with standard MOS process technology.

Method of forming a metal silicide gate in a standard MOS process sequence

The filling of sub-0.25 &mgr;m trenches with dielectric material may lead to the formation of a void. Typically, the void may be closed by oxidation. When the trench includes non-oxidizable sidewall portions, insufficient closure may result. Therefore, an oxidizable spacer layer is conformally deposited prior to depositing the bulk dielectric, so that the sidewalls of the trench may be oxidized along the entire depth of the trench, thereby allowing the complete closure of the void.

Method of filling an opening in a material layer with an insulating material

A transistor formed on a substrate comprises a gate electrode having a lateral extension at the foot of the gate electrode that is less than the average lateral extension of the gate electrode. The increased cross-section of the gate electrode compared to the rectangular cross-sectional shape of a prior art device provides for a significantly reduced gate resistance while the effective gate length, i.e., the lateral extension of the gate electrode at its foot, may be scaled down to a size of 100 nm and beyond. Moreover, a method for forming the field effect transistor described above is disclosed.

Field effect transistor with reduced gate delay and method of fabricating the same

A method of forming oxide layers of different thickness on a substrate is described, wherein the oxide layers preferably serve as gate insulation layers of field effect transistors. The method allows to form very thin, high quality oxide layers with a reduced number of masking steps compared to the conventional processing, wherein the thickness difference can be maintained within a range of some tenths of a nanometer. The method substantially eliminates any high temperature oxidations and is also compatible with most chemical vapor deposition techniques used for gate dielectric deposition in sophisticated semiconductor devices.

Method of forming layers of oxide on a surface of a substrate

A field effect transistor comprises a gate electrode contact of a highly conductive material that contacts the gate electrode and extends in the transistor width dimension at least along a portion of the channel. Thus, the gate resistance and the gate signal propagation time for a voltage applied to the gate contact is significantly reduced even for devices with an extremely down scaled gate length. Moreover, a method for fabricating the above FET is disclosed.

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Boxdorf, Germany

Stephan Kruegel