Racyics Gmbh

Infineon Technologies Ag

Stephan Henker

Sebastian Höppner

Jörg Schreiter

André Scharfe

René Schueffny

Monika Dietrich

A slew-limited output driver circuit facilitates finding a circuitry that allows a flexible setting of the slew-rate of an integrated circuit, with only a small footprint and latency, and which allows realizing different driver modes without additional components integrated protection against ESD. A short circuit will be solved by a slew-limited output driver circuit comprising a switchable current mirror providing an output current equal to an input current, wherein the current mirror is controlled by an additional switch, which is switched in response to control signals and/or an output current level of the output driver circuit, wherein adjustable operating modes of the slew-limited output driver circuit are realized by the control signals.

Slew-limited output driver circuit

An apparatus and a method for generation and adaptive regulation of body bias voltages of an integrated circuit efficiently generates control voltages for active body biasing The apparatus includes a digital circuit, a counter, a control unit and at least one charge pump. The control unit and the digital circuit are connected in a closed control loop, and the digital circuit comprises at least one hardware performance monitor to monitor a timing of a body bias voltage. The control loop is formed by a control path comprising the at least one charge pump, the hardware performance monitor and the control unit. The charge pump is controllably connected to the control unit to adjust the charge pump for generation and adaptive regulation of the body bias voltage according to a timing frequency difference between an output signal of the hardware performance monitor and a reference clock signal.

Apparatus and method for generation and adaptive regulation of control voltages in integrated circuits with body biasing or back-biasing

A method is provided for setting an initial value on a charge-storage element. A circuit includes at least one charge-storage element with at least one signal node coupled to at least one reset circuit that is associated with the charge-storage element. A diode can be included between the charge-storage element and the reset circuit. Initially, an initial potential is applied to the at least one signal node during a setting phase by connecting the at least one signal node to the initial potential. A rest potential can then be applied to the signal node during a subsequent holding phase.

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Nossen, Germany

Stephan Henker