International Business Machines Corporation

Texas Instruments Corporation

Advanced Micro Devices Corporation

Samsung Electronics Co., Ltd.

Globalfoundries Inc.

Chartered Semiconductor Manufacturing Ltd (corporation)

Stephan Grunow

Andrew Herbert Simon

Ronald G Filippi

Griselda Bonilla

Kaushik Chanda

Satyavolu Srinivas Papa Rao

Naftali Eliahu Lustig

Samuel S Choi

Phillip D Matz

Lawrence Alfred Clevenger

Theodorus E Standaert

Kevin Shawn Petrarca

Kaushik Arun Kumar

Noel M Russell

Ping-Chuan Wang

Sujatha Sankaran

Junjing Bao

David Lee Rath

Chao-Kun Hu

Sameer Kumar Ajmera

Vidhya Ramachandran

Tibor Bolom

Montray Leavy

Kangguo Cheng

Johnathan E Faltermeier

Roger Allan Quon

Dan Moy

Darius Lammont Crenshaw

Chih-Chao Yang

Jeffrey P Gambino

Huilong Zhu

Daniel C Edelstein

Yun Yu Wang

Shom Ponoth

Sanjeev Aggarwal

Sanjay C Mehta

Zhengwen O Li

John Anthony Fitzsimmons

Richard Paul Volant

Yiheng Xu

Tien-Jen Cheng

Paul Stephen McLaughlin

Kenneth D Brennan

Henry Atkinson Nye, Iii

Duofeng Yue

Samuel Sung Shik Choi

James D Werking

Somit Joshi

Edward Raymond Engbrecht

Kaushik Chandra

Yuri E Solomentsev

Valli Arunachalam

Tien Cheng

Zhiguo Sun

Wei-tsui Tseng

Hyeok-sang Oh

A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region.

Stacked via structure for metal fuse applications

A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current.

Back-end electrically programmable fuse

Structure providing more reliable fuse blow location, and method of making the same. A vertical metal fuse blow structure has, prior to fuse blow, an intentionally damaged portion of the fuse conductor. The damaged portion helps the fuse blow in a known location, thereby decreasing the resistance variability in post-blow circuits. At the same time, prior to fuse blow, the fuse structure is able to operate normally. The damaged portion of the fuse conductor is made by forming an opening in a cap layer above a portion of the fuse conductor, and etching the fuse conductor. Preferably, the opening is aligned such that the damaged portion is on the top corner of the fuse conductor. A cavity can be formed in the insulator adjacent to the damaged fuse conductor. The damaged fuse structure having a cavity can be easily incorporated in a process of making integrated circuits having air gaps.

Metal fuse structure for improved programming capability

E-fuse structures in back end of the line (BEOL) interconnects and methods of manufacture are provided. The method includes forming an interconnect via in a substrate in alignment with a first underlying metal wire and forming an e-fuse via in the substrate, exposing a second underlying metal wire. The method further includes forming a defect with the second underlying metal wire and filling the interconnect via with metal and in contact with the first underlying metal wire thereby forming an interconnect structure. The method further includes filling the e-fuse via with the metal and in contact with the defect and the second underlying metal wire thereby forming an e-fuse structure.

E-fuse structures and methods of manufacture

A metal fuse structure using redundant vias formed on one metal level in a stacked via metal fuse structure to force failures to occur in the metal level that does not have the redundant vias. The metal fuse structure includes a first dielectric layer having a conductor, a second dielectric layer above the first dielectric layer having a first conductive line and a first via, the first via is on the conductor, the first conductive line is on the first via, the first via is the only electrical connection between the first conductive line and the conductor, and a third dielectric layer above the second dielectric layer having a second conductive line, a second via and a third via, the second via and the third via are both on the first conductive line, the second conductive line is on both the first via and the second via.

Redundant via structure for metal fuse applications

A fuse structure includes within an aperture within a dielectric layer located over a substrate that exposes a conductor contact layer within the substrate a seed layer interposed between the conductor contact layer and another conductor layer. The seed layer includes a doped copper material that includes a dopant immobilized predominantly within the seed layer. The fuse structure may be severed while not severing a conductor interconnect structure also located over the substrate that exposes a second conductor contact layer within a second aperture. In contrast with the fuse structure that includes the doped seed layer having the immobilized dopant, the interconnect structure includes a doped seed layer having a mobile dopant.

Fuse and integrated conductor

The invention is directed to a method for removing copper oxide from a copper surface to provide a clean copper surface, wherein the method involves exposing the copper surface containing copper oxide thereon to an anhydrous vapor containing a carboxylic acid compound therein, wherein the anhydrous vapor is generated from an anhydrous organic solution containing the carboxylic acid and one or more solvents selected from hydrocarbon and ether solvents.

Method for removing copper oxide layer

A method of forming a semiconductor device includes patterning a photoresist layer formed over a homogeneous semiconductor device layer to be etched; subjecting the semiconductor device to an implant process that selectively implants a sacrificial etch stop layer that is self-aligned in accordance with locations of features to be etched within the homogeneous semiconductor device layer, and at a desired depth for the features to be etched; etching a feature pattern defined by the patterned photoresist layer into the homogenous semiconductor device layer, stopping on the implanted sacrificial etch stop layer; and removing remaining portion of the implanted sacrificial etch stop layer prior to filling the etched feature pattern with a fill material.

Self-aligned patterned etch stop layers for semiconductor devices

A method for capping lines includes forming a metal film layer on a copper line by a selective deposition process, the copper line disposed in a dielectric substrate, wherein the depositing also results in the deposition of stray metal material on the surface of the dielectric substrate, and etching with an isotropic etching process to remove a portion of the metal film layer and the stray metal material on the surface of the dielectric substrate, wherein the metal film layer is deposited at an initial thickness sufficient to leave a metal film layer cap remaining on the copper line following the removal of the stray metal material.

Capping of copper interconnect lines in integrated circuit devices

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Poughkeepsie, NY, United States of America

Stephan Grunow