Freescale Semiconductor,inc.

Nxp Usa, Inc.

Stephan G Mueller

Manfred P Thanner

Michael Rohleder

Gary Hay

Anthony M Reipold

Thomas Henry Luedeke

Alexandre Pierre Palus

Nancy H Amedeo

Manfred Thanner

In at least one embodiment of the disclosure, a method includes detecting an error in a local memory shared by redundant computing modules executing in delayed lockstep. The method includes pausing execution in the redundant computing modules and handling the error of the local memory. The method includes resuming execution in delayed lockstep of the redundant computing modules in response to the handling of the error.

Multi-channel network-on-a-chip

A system on chip comprises a responder unit comprising a set of responder elements and an access control unit associated with an authorization list and the responder unit. An entry of the authorization list defines a set of access requirements in relation to an address space identifying at least part of the responder unit. The access control unit is arranged to: receive a request for access to a target responder element among the responder elements of the responder unit, determine the corresponding set of access requirements for the received access request from the authorization list, and evaluate the request for access with respect to the determined set of access requirements and generate a first request evaluation result. A protection unit associated with the responder unit is arranged to: provide a group assignment assigning a group to each of the responder elements of the responder unit, provide a group authorization list, an entry of the group authorization list defining a set of group access requirements for the group assigned, receive the request for access to the target responder element, determine the group assigned to the target responder element from the group assignment and further determine the set of group access requirements from the group authorization list for the group assigned. The system-on-chip also evaluates the request with respect to the determined set of group access requirements and generates a second request evaluation result. Interaction with the target responder element is controlled in response to the first and/or second evaluation result.

System on chip and method therefor

An integrated circuit device comprising at least one memory interface module arranged to be operably coupled between at least one data storage device and a plurality of master devices within a data processing system. The at least one memory interface module comprises a plurality of buffers and at least one data access control module. The at least one data access control module being arranged to fetch data from the at least one data storage device in response to a received memory access request comprising a master device identifier, select at least one buffer based at least partly on the master device identifier of the received access request, and load the fetched data into the selected at least one buffer.

Integrated circuit device and method for providing data access control

A system for distributing an available memory resource comprising at least two random access memory (RAM) elements and RAM routing logic. The RAM routing logic comprises configuration logic to dynamically distribute the available memory resource into a first memory area providing redundant memory storage and a second memory area providing non-redundant memory storage. The system may further comprise bus access ports which support at least one of concurrent access by a bus access port to access redundantly stored data or non-redundantly stored data, or concurrent access by at least two bus access ports to respective RAM elements to access redundantly stored data or to a respective one of the RAM elements to access non-redundantly stored data. Comparison logic and error detection or correction logic may be provided to detect or correct errors in information read from the RAM elements.

System for dynamically distributing an available memory resource to redundant and non-redundant storage areas using RAM routing logic

A system comprises a first master element; and at least one shared communication element arranged to operably couple the first master element to at least one slave element. The system further comprises at least one validation element located on at least one further validation path located between the first master element and the at least one slave element, wherein the at least one validation element is arranged to validate at least one of: at least one access request by the first master element; and a response to an access request from the at least one slave element.

Processor based system having ECC based check and access validation information means

A system comprises at least two random access memory (RAM) elements arranged to store data redundantly. The system further comprises RAM routing logic comprising comparison logic operably coupled to the at least two RAM elements and arranged to compare redundant data read from the at least two RAM elements, and check and validation logic, independent of the RAM routing logic, operably coupled to the at least two RAM elements and arranged to additionally detect an error in the redundant data read from the at least two RAM elements and provide an error indication signal to the RAM routing logic in response thereto. The RAM routing logic further comprises selection logic arranged to dynamically select redundant data from one of the at least two RAM elements based on the comparison of the redundant data and the error indication signal.

Growing community of inventors

Taunusstein, Germany

Stephan G Mueller