Advanced Micro Devices Corporation

Apple Inc.

Telefonaktiebolaget Lm Ericsson (publ)

Globalfoundries Inc.

Ericsson Ab

Redback Networks Inc.

Stephan G Meier

Tyler J Huberty

Gerard Richard Williams

Norbert Juffa

Stuart F Oberman

Ramsey W Haddad

James B Keller

Frederick Daniel Weber

Robert G Hathaway

Mridul Agarwal

Pradeep Kanapathipillai

John Gregory Favor

Sandeep Kumar Gupta

Evan Gewirtz

Derrick R Meyer

John H Mylius

Srinivasa Rangan Sridharan

Nikhil Gupta

Suparn Vats

Edmund G Chen

Jeffrey E Trull

Eric Jason Furbish

Edward Ho

Vivek Venkatraman

Scott A White

Hari Kannan

David S Christie

Gene W Shen

James K Pickett

Kevin John McGrath

Brian D McMinn

Marius Evers

Gideon N Levinsky

Bruce Alan Gieseke

Brian Alleyne

Paul S Keltcher

Michael Feng

Michael David Achenbach

Kulin N Kothari

Edmund C Chen

Francesco Spadini

William McGee

Chetana Nagendra Keltcher

Onur Mutlu

Pavlos Konas

Eric Trehus

Khubaib Khubaib

Leslie A Barnes

Jayaram Beladakere

Manu Gulati

Minesh H Patel

Jeremie S Kim

Gerard R Williams Iii

A cache may store critical cache lines and non-critical cache lines, and may attempt to retain critical cache lines in the cache by, for example, favoring the critical cache lines in replacement data updates, retaining the critical cache lines with a certain probability when victim cache blocks are being selected, etc. Criticality values may be retained at various levels of the cache hierarchy. Additionally, accelerated eviction may be employed if the threads previously accessing the critical cache blocks are viewed as dead.

Mitigating retention of previously-critical cache lines

Criticality-informed caching policies

In an embodiment, a processor includes a plurality of prefetch circuits configured to prefetch data into a data cache. A primary prefetch circuit may be configured to generate first prefetch requests in response to a demand access, and may be configured to invoke a second prefetch circuit in response to the demand access. The second prefetch circuit may implement a different prefetch mechanism than the first prefetch circuit. If the second prefetch circuit reaches a threshold confidence level in prefetching for the demand access, the second prefetch circuit may communicate an indication to the primary prefetch circuit. The primary prefetch circuit may reduce a number of prefetch requests generated for the demand access responsive to the communication from the second prefetch circuit.

Secondary prefetch circuit that reports coverage to a primary prefetch circuit to limit prefetching by primary prefetch circuit

Techniques are disclosed for obtaining data using memory timing characteristics. In some embodiments, a physical unclonable function is used to obtain the data. In various embodiments, a computer system programs a timing parameter of a memory accessible by the computer system to a value that is outside of a specified operable range for the timing parameter. In various embodiments, the computer system performs one or more memory operations to a least a portion of the memory and detects a pattern of errors in the portion of the memory. In some embodiments, the computer system generates a response dependent on the pattern of errors. The response may be used to identify the computer system.

Security techniques based on memory timing characteristics

In an embodiment, a processor may implement an access map-pattern match (AMPM)-based prefetch circuit for a multi-level cache system. The access patterns that are matched to the access maps may include prefetches for different cache levels. Centralizing the generation of prefetches into one prefetch circuit may provide better observability and controllability of prefetching at various levels of the cache hierarchy, in an embodiment. Prefetches at different levels may be controlled individually based on the accuracy of those prefetches, in an embodiment. Additionally, in an embodiment, access patterns that are longer that a given threshold may have the granularity of the prefetches change so that more data is prefetched and the prefetches occur farther in advance, in some embodiments.

Unified prefetch circuit for multi-level caches

Systems, apparatuses, and methods for optimizing a load-store dependency predictor (LSDP). When a younger load instruction is issued before an older store instruction and the younger load is dependent on the older store, the LSDP is trained on this ordering violation. A replay/flush indicator is stored in a corresponding entry in the LSDP to indicate whether the ordering violation resulted in a flush or replay. On subsequent executions, a dependency may be enforced for the load-store pair if a confidence counter is above a threshold, with the threshold varying based on the status of the replay/flush indicator. If a given load matches on multiple entries in the LSDP, and if at least one of the entries has a flush indicator, then the given load may be marked as a multimatch case and forced to wait to issue until all older stores have issued.

Load/store dependency predictor optimization for replayed loads

In an embodiment, a processor may implement an access map-pattern match (AMPM)-based prefetch circuit with features designed to improve prefetching accuracy and/or reduce power consumption. In an embodiment, the prefetch circuit may be configured to detect that pointer reads are occurring (e.g. 'pointer chasing.') The prefetch circuit may be configured to increase the frequency at which prefetch requests are generated for an access map in which pointer read activity is detected, compared to the frequency at which the prefetch requests would be generated in the pointer read activity is not generated. In an embodiment, the prefetch circuit may also detect access maps that are store-only, and may reduce the frequency of prefetches for store only access maps as compared to the frequency of load-only or load/store maps.

Prefetch circuit for a processor with pointer optimization

A prefetch circuit may include a memory, each entry of which may store an address and other prefetch data used to generate prefetch requests. For each entry, there may be at least one 'quality factor' (QF) that may control prefetch request generation for that entry. A global quality factor (GQF) may control generation of prefetch requests across the plurality of entries. The prefetch circuit may include one or more additional prefetch mechanisms. For example, a stride-based prefetch circuit may be included that may generate prefetch requests for strided access patterns having strides larger than a certain stride size. Another example is a spatial memory streaming (SMS)-based mechanism in which prefetch data from multiple evictions from the memory in the prefetch circuit is captured and used for SMS prefetching based on how well the prefetch data appears to match a spatial memory streaming pattern.

Prefetch circuit with global quality factor to reduce aggressiveness in low power modes

In an embodiment, a system may include multiple processors and a cache coupled to the processors. Each processor includes a data cache and a prefetch circuit that may be configured to generate prefetch requests. Each processor may also generate memory operations responsive to cache misses in the data cache. Each processor may transmit the prefetch requests and memory operations to the cache. The cache may queue the memory operations and prefetch requests, and may be configured to detect, on a per-processor basis, occupancy in the queue of memory requests and low confidence prefetch requests from the processor. The cache may determine if the per-processor occupancies exceed one or more thresholds, and may generate a throttle control to the processors responsive to the occupancies. In an embodiment, the cache may generate the throttle control responsive to a history of the last N samples of the occupancies.

Prefetch throttling in a multi-core system

In a content-directed prefetcher, a pointer detection circuit identifies a given memory pointer candidate within a data cache line fill from a lower level cache (LLC), where the LLC is at a lower level of a memory hierarchy relative to the data cache. A pointer filter circuit initiates a prefetch request to the LLC candidate dependent on determining that a given counter in a quality factor (QF) table satisfies QF counter threshold value. The QF table is indexed dependent upon a program counter address and relative cache line offset of the candidate. Upon initiation of the prefetch request, the given counter is updated to reflect a prefetch cost. In response to determining that a subsequent data cache line fill arriving from the LLC corresponds to the prefetch request for the given memory pointer candidate, a particular counter of the QF table may be updated to reflect a successful prefetch credit.

Content-directed prefetch circuit with quality filtering

Systems, methods, and apparatuses for reducing the load to load/store address latency in an out-of-order processor. When a producer load is detected in the processor pipeline, the processor predicts whether the producer load is going to hit in the store queue. If the producer load is predicted not to hit in the store queue, then a dependent load or store can be issued early. The result data of the producer load is then bypassed forward from the data cache directly to the address generation unit. This result data is then used to generate an address for the dependent load or store, reducing the latency of the dependent load or store by one clock cycle.

Reducing latency for pointer chasing loads

Methods and processors for managing load-store dependencies in an out-of-order instruction pipeline. A load store dependency predictor includes a table for storing entries for load-store pairs that have been found to be dependent and execute out of order. Each entry in the table includes hashed values to identify load and store operations. When a load or store operation is detected, the PC and an architectural register number are used to create a hashed value that can be used to uniquely identify the operation. Then, the load store dependency predictor table is searched for any matching entries with the same hashed value.

Load-store dependency predictor PC hashing

Methods and processors for enforcing an order of memory access requests in the presence of barriers in an out-of-order processor pipeline. A speculative color is assigned to instruction operations in the front-end of the processor pipeline, while the instruction operations are still in order. The instruction operations are placed in any of multiple reservation stations and then issued out-of-order from the reservation stations. When a barrier is encountered in the front-end, the speculative color is changed, and instruction operations are assigned the new speculative color. A core interface unit maintains an architectural color, and the architectural color is changed when a barrier retires. The core interface unit stalls instruction operations with a speculative color that does match the architectural color.

Processor and method for implementing barrier operation using speculative and architectural color values

Growing community of inventors

Mountain View, CA, United States of America

Stephan G Meier