Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Commissariat a L'energie Atomique

Aledia

Stephan Borel

Thomas Ernst

Thibaut Sohier

Lucas Duperrex

Henri Sibuet

Bruno Reig

Christel Dieppedale

Jean Charbonnier

Bertrand Chambion

Brigitte Soulier

Vincent Beix

Thomas Lacave

Jean-Philippe Michel

Fabienne Goutaudier

Gilles Simon

Thibault Sohier

Device of the chip or electronic system-in-package type, comprising at least one element for protecting at least part of at least one face of the device, said protective element comprising at least:

Chip or system-in-package protection using the GMI effect

An electronic system in package, including at least: a support; one or more chips mechanically and electrically coupled to a front face of the support; an encapsulation material covering the front face of the support and encapsulating the chip(s); several side protection elements, comprising an opaque material and laterally surrounding the chip(s) and configured to form a barrier at least against laser attacks made through side faces of the electronic system in package that are substantially perpendicular to the front face of the support; and wherein the side protection elements are disposed in the encapsulation material or in one or more first blocks of material distinct from the support and disposed in the encapsulation material.

Electronic system in package comprising protected side faces

An electronic chip includes at least an electronic circuit disposed on a front face of a substrate; and an embrittlement structure comprising at least blind holes, each extending through a rear face of the substrate and a portion of the thickness of the substrate and each having a section, in a plane parallel to the rear face of the substrate, of surface area S and having a closed outer contour, the shape of which includes at least one radius of curvature R, such that S&#x3e;&#x3c0;&#xb7;R.

Electronic chip, the rear face of which is protected by an improved embrittlement structure

Electronic chip with protected rear face

An electronic circuit including a semiconducting or conducting substrate having first and second opposite surfaces and at least first and second non-parallel electrically insulating trenches that extend from the first surface in the substrate, define at least one portion of the substrate and join at a junction, the portion of the substrate including a protrusion that extends to the junction.

Electronic circuit comprising electrically insulating trenches

A method of making connection elements for a microelectronic device is provided, including foil ling a conducting layer on a support on which there is at least one conducting pad located on a front face of the support opposite a back face thereof, the conducting layer including a first conducting portion in contact with at least one conducting pad, the first conducting portion extending on the front face and being connected to at least one second conducting portion extending in contact with at least one given wall of the support being located between the front and back faces and forming a non-zero angle with the front face; thinning the support at the back face to release one conducting end of the second conducting portion as a free conducting end projecting from the back face; and after the thinning, bending the free conducting end projecting from the back face.

Making interconnections by curving conducting elements under a microelectronic device such as a chip

An electronic chip and a method of making thereof is provided, where the electronic chip includes at least: an electronic circuit arranged at a front face of a substrate; a first protective layer arranged on a rear face of the substrate; a resistive element arranged on the first protective layer and facing at least one part of the electronic circuit, mechanically supported by the first protective layer and connected electrically and/or in an inductive manner to the electronic circuit; a second protective layer covering at least the resistive element; and in which the first protective layer comprises at least one dielectric material having a resistance to chemical etching by at least one chemical etching agent less than or equal to that of a dielectric material of the second protective layer.

Electronic chip comprising multiple layers for protecting a rear face

The fabrication of a semiconductor fixed structure defining a volume, for example of a MEMS micro electro-mechanical system includes, determining thicknesses beforehand depending on the functional distances associated with elements. At least one element is formed on a substrate by thermal oxidation of the substrate so as to form an oxide layer followed by selective etching of the oxide layer so as to define the volume in an etched portion by baring the underlying substrate so as to define the element in an unetched portion, and later oxidation of the substrate so as to form an oxide layer, in order to obtain the elements at the functional distances.

Method for fabricating a fixed structure defining a volume receiving a movable element in particular of a MEMS

The disclosure concerns a microelectronic device provided with one or more &#x3c;&#x3c;quantum wires&#x3e;&#x3e;, able to form one or more transistor channels, and optimized in terms of arrangement, shape or/and composition. The invention also uses a method for fabricating said device, comprising the steps of: the forming, in one or more thin layers resting on a support, of a first block and a second block in which at least one transistor drain region and at least one transistor source region are respectively intended to be formed, and of a structure connecting the first block to the second block, and the forming, on the surface of the structure, of wires connecting a first region of the first block with another region of the second block which faces the first region.

Structure and method for fabricating a microelectronic device provided with one or more quantum wires able to form one or more transistor channels

A microelectronic device provided with one or more quantum wires, able to form one or more transistor channels, and optimized in terms of arrangement, shape, and/or composition. A method for fabricating the device includes forming, in one or more thin layers resting on a support, a first block and a second block in which at least one transistor drain region and at least one transistor source region are respectively intended to be formed, forming a structure connecting the first block to the second block, and forming, on the surface of the structure, wires connecting a first region of the first block with another region of the second block that faces the first region.

Structure and method for realizing a microelectronic device provided with a number of quantum wires capable of forming one or more transistor channels

The invention relates to a field-effect microelectronic device, as well as the method of production thereof. The device includes a substrate as well as at least one improved structure capable of forming one or more transistor channels. This structure, formed by a plurality of bars stacked on the substrate, can make it possible to save space in the integration of field-effect transistors as well as to improve the performance thereof.

Field-effect microelectronic device, capable of forming one or several transistor channels

The invention relates to a field-effect microelectronic device, and the production method thereof. Said device comprises a substrate () and at least one improved structure (), capable of forming one or several transistor channels. Said structure, composed of several bars stacked on the substrate, may allow space saving in the integration of field-effect transistors and the performances thereof to be improved.

Growing community of inventors

Crolles, France

Stephan Borel