Siemens Aktiengesellschaft

Infineon Technologies Ag

Infineon Technologies Austria Ag

Stephan Auer

Armin Kohlhase

Hanno Melzner

Horst Theuss

Klaus Elian

Guenther Ruhl

Jochen Dangelmaier

Franz Michael Darrer

Mathias Vaupel

Christoph Sandner

Manfred Fries

Thomas Mueller

Josef Höglauer

Tue Fatt David Wee

Matthias Rose

Roman Riederer

Sie Boo Chiang

A sensor arrangement according to an embodiment includes a substrate, and at least one sensor and a control circuit mounted on the substrate, wherein the at least one sensor and the control circuit are located on the substrate to be mountable inside a battery cell and outside the battery cell, respectively.

Sensor arrangement, battery cell and energy system

A power converter is described that includes components arranged within a first die and a second die of a single package. The first die includes one or more first switches coupled to a switching node of a power stage. The second die includes one or more second switches coupled to the switching node of the power stage, a feedback control unit configured to detect a current level at the one or more second switches of the power stage, and a controller unit configured to control the one or more first switches and the one or more second switches of the power stage based at least in part on the current level detected by the feedback control unit.

Switched-mode power converter with split partitioning

A semiconductor memory configuration and a manufacturing process for the semiconductor memory configuration use a polishing process in the manufacture of a semiconductor memory configuration with stacked-capacitor-above-bit-line memory cells. At least TC pillars are created with the aid of a CMP step and a completely planarized surface existing prior to the manufacture of the bit line. Further CMP steps are advantageously used, inter alia, in the manufacture of a TB pillar of a bit line which is countersunk in a trench and of a lower capacitor plate, as well as to completely planarize a cell array and a periphery prior to interconnection of the circuit.

Semiconductor memory device having a transistor, a bit line, a word line

Integrated semiconductor circuit or micromechanical component and

Growing community of inventors

Dachau, Germany

Stephan Auer