Sun Microsystems, Inc.

Oracle America, Inc.

Dolphin Interconnect Solutions, Inc.

Steinar Forsmo

Morten Schanke

Hans Rygh

Ola Torudbakken

Bjorn Dag Johnsen

Ola Tørudbakken

Christopher J Jackson

David Brean

Ali Bozkaya

Knut Tvete

Ola Torudbaken

Ola Torudrakken

Hans Rygn

One embodiment of the invention provides a method of operating a switch in a communications network. The method includes storing a set of routings for each port in the switch. When a packet is received at a port in the switch, the set of routings corresponding to the port at which the packet was received is accessed. A port from which to forward the packet from the switch is determined in accordance with the set of routings. The packet is then duly forwarded over the network from the port as determined by the routings.

Switching method and apparatus for use in a communications network

There is described an apparatus and method for implementing a communications port. The apparatus comprises a core, which is operable to divide the port into a plurality of sub-ports by dividing a data transfer capacity of the port among the plurality of sub-ports using time division multiplexing. Each sub-port is allocated a corresponding data transfer capacity.

Apparatus and method for a core for implementing a communications port

An Infiniband switch can be provided. The switch can have an input port logic unit for determining an output virtual lane for a received packet and for storing a descriptor of the determined output virtual lane in a packet field not protected by a checksum field of the packet. The switch can also have a routing unit for transferring the received packet to an output port corresponding to the determined output virtual lane. Additionally, the switch can have an output port logic unit for simultaneously checking the integrity of the packet transferred through the routing unit and calculating a new value for the checksum with the descriptor moved to a correct packet field, which field is included in the calculation of the checksum.

VCRC checking and generation

An Infiniband device is provided. The device has a plurality of input/output ports. Each port has associated therewith an input buffer for storage of a packet received at that port. Each port also has associated therewith a plurality of output buffers for storage of a packet transmitted from an input buffer via a switching matrix. Each port is arranged to share its associated plurality of output ports with at least one other port. Each input buffer is also associated with a single output buffer of each shared plurality of output buffers. A packet received at an input buffer is transmitted to all associated output buffers via the switching matrix in parallel with an output buffer select signal. The output buffer select signal is sent to less than all of the associated output buffers, any output buffer not receiving the output buffer select signal is configured to discard the packet transmitted from the input buffer.

Input and output buffering

An Infiniband device can be provided. The device can have an input port for receiving a packet. The port can be operable to extract a destination descriptor and a quality of service requirement descriptor for the packet and simultaneously to determine an output port of the device for onward transmission of the packet on the basis of the destination descriptor and to determine an output port virtual lane for each output port of the device on the basis of the quality of service requirement descriptor. The port can additionally be operable subsequently to use the determined output port to select between the determined output port virtual lanes.

Service level to virtual lane mapping

A receiver for digital data is provided. The receiver comprises a ring buffer operable to store received data. The receiver also comprises a write pointer controller for the buffer, operable to control the writing of received data into the buffer, and a read pointer controller for the buffer, operable to control the reading of data from the buffer. The receiver further comprises a pointer adjustment controller operable, in response to a detection of a special data indicator, to control at least one of the write pointer controller and the read pointer controller using forward looking operable to foresee a data location within the buffer corresponding to a future read location of the buffer.

Data transfer

A scalable coherent interface (SCI) architecture delivers a high speed unidirectional signal from one SCI node to a next successive SCI node. The signal includes a data portion, e.g., SCI symbol, and a clock portion, e.g., a symbol separator. The clock portion indicates when the data portion may be sampled when collecting a sequence of SCI symbols. Relative timing between bits of the data portion and between the data portion as a whole and the symbol separator clock becomes skewed during transmission. The receiving node introduces delay in the clock portion as a function of detected stability in a synchronizing packet. A plurality of data registers are cyclicly written in response to the delayed clock portion whereby a single one of said registers at a given time is concurrently clocked and enabled. A control device monitors enable signals applied to the registers and in coordinated fashion cyclically reads SCI symbols therefrom. As a result, signal transmission from a transmitting time domain to a receiving time domain includes a time domain mapping and de-skewing function.

Growing community of inventors

Oslo, Norway

Steinar Forsmo