Infineon Technologies Ag

Infineon Technologies Austria Ag

Steffen Thiele

Andreas Peter Meiser

Franz Hirler

Aron Theil

Markus Zundel

Rainald Sander

Carlos Joao Marques Martins

Marcus Nuebling

Thomas Bemmerl

Stefan Macheiner

Markus Winkler

Carmelo Giunta

A driver device includes: a voltage terminal; a ground terminal; an output terminal; a first nMOS power transistor having a drain electrically connected to the voltage terminal, a source electrically connected to the output terminal, and a gate; an overvoltage protection circuit configured to limit a gate-to-source voltage of the first nMOS power transistor in a normal operating mode for the driver device; a pulldown circuit configured to force the first nMOS power transistor off in a stress test mode for the driver device; and a blocking circuit configured to block current flow from the output terminal to the ground terminal through the overvoltage protection circuit and the pulldown circuit in the stress test mode. A method of stress testing the driver device is also described.

Driver device having an NMOS power transistor and a blocking circuit for stress test mode, and method of stress testing the driver device

A semiconductor device includes a first chip pad, a power semiconductor chip arranged on the first chip pad and including at least a first and a second power electrode, and a clip connected to the first power electrode. In this case, an integral part of the clip forms a shunt resistor and a first contact finger of the shunt resistor is embodied integrally with the clip.

Semiconductor device with integrated shunt resistor

Disclosed is a method, a circuit arrangement, and an electronic circuit. The method includes discharging a gate-source capacitance of a transistor device from a first voltage level to a second voltage level with a first resistor connected in parallel with the gate-source capacitance and measuring a first discharging time associated with the discharging, and discharging the gate-source capacitance from the first voltage level to the second voltage level with the first resistor and a second resistor connected in parallel with the gate-source capacitance and measuring a second discharging time associated with the discharging. The method further includes comparing a ratio between the first discharging time and the second discharging time with a predefined threshold, and detecting a fault based on the comparing.

Evaluating a gate-source leakage current in a transistor device

A switched-mode power converter includes an inductive storage element and a cascode circuit. The cascode circuit includes a double-gate field effect transistor. A switchable load path of the double-gate field effect transistor is electrically connected in series with the inductive storage element.

Switched-mode power converter with an inductive storage element and a cascode circuit

An integrated semiconductor device is provided. According to an embodiment, the integrated semiconductor device includes a semiconductor body having a first surface with a normal direction defining a vertical direction, an opposite surface, a first area including a vertical power field-effect transistor structure, a second area including a three-terminal step-down level-shifter, and a third area including a three-terminal step-up level-shifter. A terminal of the vertical power field-effect transistor structure is electrically connected with one of the three-terminal step-down level-shifter and the three-terminal step-up level-shifter.

Integrated semiconductor device having a level shifter

A power transistor has a semiconductor body with a bottom side and top side spaced distant from the bottom side in a vertical direction. The semiconductor body includes a plurality of transistor cells, a source zone of a first conduction type, a body zone of a second conduction type, a drift zone of the first conduction type, a drain zone, and a temperature sensor diode having a pn-junction between an n-doped cathode zone and a p-doped anode zone. The power transistor also has a drain contact terminal on the top side, a source contact terminal on the bottom side, a gate contact terminal, and a temperature sense contact terminal on the top side. Depending on the first and second conduction types the anode or cathode zone is electrically connected to the source contact terminal and the other diode zone is electrically connected to the temperature sense contact terminal.

Power transistor with integrated temperature sensor element, power transistor circuit, method for operating a power transistor, and method for operating a power transistor circuit

A testing device in accordance with various embodiments may include: a plurality of first terminals configured to be connected to a plurality of devices-under-test, wherein each first terminal of the plurality of first terminals may be configured to be connected to a respective device-under-test of the plurality of devices-under-test; a signal interface configured to be connected to a tester; and a circuit configured to exchange an identical first signal with each device-under-test of the plurality of devices-under-test through a respective first terminal of the plurality of first terminals, and to exchange at least one interface signal with the tester through the signal interface.

Testing device and a circuit arrangement

A circuit is provided, including a first resistor, a second resistor which may have an adjustable resistance, and a control unit. The control unit may be configured to adjust the second resistor to have a first resistance at which a voltage due to a first current flowing through the first resistor is equal to a voltage due to a second current flowing through the second resistor. The control unit may be further configured to adjust the second resistor to have a second resistance at which a voltage due to another first current different from the first current and flowing through the first resistor is equal to the voltage due to the second current flowing through the second resistor. The control unit may be further configured to adjust the second resistor to have a third resistance based on at least a difference of the first resistance and the second resistance.

Circuits and methods for measuring a current

A bridge circuit is provided. The bridge circuit includes a first integrated semiconductor device having a high-side switch, a second integrated semiconductor device having a low-side switch electrically connected with the high-side switch, a first level-shifter electrically connected with the high-side switch and integrated in one of the first integrated semiconductor device and the second integrated semiconductor device, and a second level-shifter electrically connected with the low-side switch and integrated in one of the first integrated semiconductor device and the second integrated semiconductor device. Further, an integrated semiconductor device is provided.

Integrated semiconductor device and a bridge circuit with the integrated semiconductor device

A semiconductor arrangement includes a first and second controllable vertical n-channel semiconductor chip. Each of the controllable vertical n-channel semiconductor chips has a front side, a rear side opposite the front side, a front side main contact arranged on the front side, a rear side main contact arranged on the rear side, and a gate contact arranged on the front side for controlling an electric current between the front side main contact and the rear side main contact. The rear side contacts of the first and second semiconductor chips are electrically connected to one another.

Semiconductor arrangement

An integrated circuit including a semiconductor device has a power component including a plurality of trenches in a cell array, the plurality of trenches running in a first direction, and a sensor component integrated into the cell array of the power component and including a sensor cell having an area which is smaller than an area of the cell array of the power component. The integrated circuit further includes isolation trenches disposed between the sensor component and the power component, an insulating material being disposed in the isolation trenches. The isolation trenches run in a second direction that is different from the first direction.

Integrated circuit, semiconductor device and method of manufacturing a semiconductor device

A semiconductor device a field of transistor cells integrated in a semiconductor body. A number of the transistor cells forming a power transistor and at least one of the transistor cells forming a sense transistor. A first source electrode is arranged on the semiconductor body electrically connected to the transistor cell(s) of the sense transistor but electrically isolated from the transistor cells of the power transistor. A second source electrode is arranged on the semiconductor body and covers the transistor cells of both the power transistor and the sense transistor, and at least partially covering the first source electrode in such a manner that the second source electrode is electrically connected only to the transistor cells of the power transistor but electrically isolated from the transistor cells of the sense transistor.

Current sense transistor with embedding of sense transistor cells

Disclosed is an electronic circuit. The electronic circuit includes a transistor having a control terminal to receive a drive signal, and a load path between a first and a second load terminal. A voltage protection circuit is coupled to the transistor, has a control input, is configured to assume one of an activated state and a deactivated state as an operation state dependent on a control signal received at the control input, and is configured to limit a voltage between the load terminals or between one of the load terminals and the control terminal. A control circuit is coupled to the control input of the voltage protection circuit and is configured to deactivate the voltage protection circuit dependent on at least one operation parameter of the transistor and when a voltage across the load path or a load current through the load path is other than zero.

Method and circuit for driving an electronic switch

A current sensing circuit arrangement is disclosed. The circuit arrangement includes a load transistor for controlling a load current to a load being coupled to a drain electrode of the load transistor. A sense transistor is coupled to the load transistor. The sense transistor has a drain electrode that provides a measurement current representative of the load current. The load transistor and the sense transistor are field effect transistors having a common source electrode. A measurement circuit is configured to receive the measurement current from the sense transistor and to generate an output signal therefrom, the output signal being representative of the load current.

Circuit arrangement including a common source sense-FET

A circuit for driving a transistor half bridge is disclosed that comprises a series circuit of a first and a second transistor both having intrinsic or external free-wheeling diodes coupled in parallel. The circuit for driving a transistor half bridge comprises: an over-current detection circuit that is configured to signal an over-current condition when a load current flowing through the first transistor exceeds a first threshold; a protection circuit that is coupled to the over-current detection circuit and that is configured to disable an activation of the first transistor in response to a detected over-current and to re-enable the activation of the first transistor after a first time interval has elapsed; an evaluation circuit that is coupled to the over-current detection circuit and that is configured to check whether a further over-current condition is detected within a second time interval that follows the first time interval. An active free-wheeling by activating the second transistor is disabled when a further over-current condition is detected within the second time interval, and an active free-wheeling by activating the second transistor is enabled during the first time interval when no further over-current condition is detected within the second time interval.

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Munich, Germany

Steffen Thiele