Infineon Technologies Ag

Steffen Sonnekalb

Bernd Meyer

Franz Klug

Berndt Gammel

Gerd Dirscherl

Jan Otterstedt

Stefan Mangard

Christian Peters

Robin Boch

Michael Goessel

Rainer Goettfert

Andreas Wenzel

Benedikt Driessen

Marcus Janke

Gunther Fenzl

Astrid Elbe

Thomas Kunemund

Joel Hatsch

Erwin Hess

Jorge Guajardo Merchan

Dirk Rabe

Stefan Ruping

Rainer Göttfert

Jürgen Birkhäuser

A storage device comprises a plurality of bitwise-modifiable memory cells. A control device is also provided, which, in order to modify existing data content written to a group of memory cells with new data content to be written, is designed to compare the existing data content and the data content to be written in order to obtain a comparison result. The control device is designed to determine a subset of the group of memory cells for modification and a remaining length based on the comparison result, and to write the data content to be written to the subset, leaving the remaining set at least partially unchanged. For modifying the existing data content, the storage device is designed to read from a memory location of the storage device and to verify the correctness of the memory location.

Storage device and method for modifying memory cells of a storage device

A data processing device including a memory having a plurality of memory locations for respectively storing a value, wherein the data processing device has, for each memory location, an associated error detection memory area, a memory controller which is configured, when a value is written to a memory location, to store an associated error detection code in the error detection memory area associated with the memory location, a memory access element, and an integrity checker configured to perform an EDC check.

Memory integrity check

A method is provided for accessing a memory via at least one address, wherein the at least one address comprises a codeword of a code. Corresponding devices are also described.

Address-coded access towards memory

A memory arrangement having a memory, a first buffer memory, a first buffer memory controller which, during the storage of memory contents from the memory in the first buffer memory, is configured to invalidate the memory contents in the memory by means of a modification, a second buffer memory and a second buffer memory controller which is configured to read memory contents from the memory, to check whether the memory contents read from the memory are valid and, if the memory contents read from the memory are invalid, to apply a reversal of the modification to the read memory contents.

Temporarily storing memory contents

A memory circuit may include a plurality of electrically programmable memory cells arranged in an electrically programmable non-volatile memory cell array along a plurality of rows and a plurality of columns, a plurality of word lines, each word line coupled with a plurality of word portions of the plurality of memory cells, each word portion configured to store a data word, and at least one overlay word line coupled with a plurality of overlay portions, each overlay portion including overlay memory cells, each of the plurality of overlay portions including an overlay word. The memory circuit is configured to read, for each of the plurality of word lines, from each of the word portions simultaneously with an overlay portion of the plurality of overlay portions, with an output of the read operation being a result of a logic operation performed on the data word and the overlay word.

Memory circuit and method of operating a memory circuit

A signature module calculates a signature during the execution of a program by a central processing unit based on program instructions to the central processing unit, and stores the signature in a signature register of the signature module. The signature module includes: a calculation unit configured to generate a signature value based on program instructions executed on the central processing unit; and an instruction information interface configured to receive at least one item of instruction information from the central processing unit which indicates whether an instruction currently being executed by the central processing unit was jumped to indirectly or directly.

Program-instruction-controlled instruction flow supervision

A method for encrypting data stored in a memory area is proposed, wherein the data are encrypted on the basis of a key identification for the data and on the basis of a one-time key.

Data encryption of a storage area

A method of sending data is provided. The method may include, executed in a master, applying a first code to an address of an addressed data sink of a slave, thereby forming a master-encoded address, combining the data with the master-encoded address using a reversible function, thereby forming a data-address-combination, and sending the data-address-combination and the address from the master to the slave.

Data encryption and verification between master and slave

A memory arrangement having a memory cell field with columns and rows of writable memory cells, a memory controller which is configured to initiate an access to a first group of memory cells of a row of memory cells and, together with the access to the first group of memory cells, to initiate a read access to a second group of memory cells of the row of memory cells, and a verification circuit which is configured to check whether the access to the first group of memory cells has been performed on the correct row of memory cells on the basis of whether values read during the read access to the second group of memory cells match values previously stored by the second group of memory cells.

Verifying memory access

An apparatus for detecting integrity violation includes a feedback shift register including a plurality of registers connected in series, and a feedback function unit connected between an output of a number of the registers and an input of at least one of the registers. The apparatus further includes an integrity violation detector adapted to determine as to whether a sequence of values at an input or output of at least one of the registers, or a logic combination thereof, is a non-constant sequence or a constant sequence. The apparatus is further adapted to output an indication that the feedback shift register is in an integral state if the sequence of values is a non-constant sequence, or to output an indication that the feedback shift register is subjected to an integrity violation if the sequence of values is a constant sequence.

Apparatus and method for detecting integrity violation

Memory circuit including overlay memory cells and method of operating thereof

A memory circuit includes electrically programmable memory cells arranged in a non-volatile memory cell array along rows and columns, word lines, each word line coupled with one or more memory cells, non-volatile marking memory cells, wherein at least one word line of the word lines is associated with one or more marking memory cells, and marking bit lines, each associated with marking memory cells, marking source lines, each associated with marking memory cells, wherein, for marking memory cells, a physical connection from an associated marking source line and/or from an associated marking bit line to the marking memory cells defines those marking memory cells to a non-changeable state, wherein the marking memory cells are configured to identify the associated word line of respective marking memory cells in the non-changeable memory state.

Memory circuit including at least one marking cell and method of operating said memory circuit

A chip is provided having processing circuits, each processing circuit configured to process a data vector to be stored according to a multiplication of the vector by a processing matrix, the sum of the processing matrices corresponding to the non-unit-matrix part of a generator matrix of a predetermined linear code in reduced form, a summing circuit to sum the results of the processing operations of the data vector, a storage circuit to store the data vector to be stored together with the sum of the generated results as one data word in a memory, a read-out circuit to read the stored data word out of the memory, and a decoding circuit to check whether the data word read out is a valid code word of the linear code and to output an error signal if the data word is not a valid code word of the linear code.

Chip and method for detecting a change of a stored data vector

A system comprising a first processor and a second processor is provided. The first processor is configured to load an instruction block from a first memory, wherein said instruction block comprises a plurality of opcodes and a stored error code. For each opcode of the plurality of opcodes of the instruction block, the first processor is configured to determine a first determined signature depending on said opcode. The first processor is configured to determine a determined error code for the instruction block depending on each opcode and depending on the first determined signature of each opcode of the plurality of opcodes of the instruction block. Moreover, the first processor is configured to determine that a first error occurred, if the determined error code is different from the stored error code. The second processor is configured to determine a second determined signature for a current opcode of the plurality of opcodes of the instruction block depending on said current opcode. Moreover, the second processor is configured to determine that a second error occurred, if the second determined signature for the current opcode is different from the first determined signature for the current opcode.

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Taufkirchen, Germany

Steffen Sonnekalb