Telefonaktiebolaget Lm Ericsson (publ)

Unwired Planet, LLC

Intel Corporation

Steffen Reinhardt

Stefan Mueller-Weinfurtner

Udo Wachsmann

Rainer Walter Bachl

Dietmar Lipka

Peter Bode

Sharon Graif

Stefan MÜLLER-Weinfurtner

A circuit arrangement may include an analog-to-digital-converter (ADC) configured to convert an analog signal into a digitized signal having an ADC frequency, a decimation circuit configured to provide a first signal having a sampling frequency based on the digitized radio signal having the ADC frequency. The sampling frequency is smaller than the ADC frequency. The circuit arrangement may further include a timer circuit providing a second signal having a timer frequency and a timing control signal to control the timing of the decimation circuit, and a difference determination circuit configured to determine a phase difference between the second signal and the first signal.

Circuit arrangement for clock synchronization

A technique for controlling a receiver to enter a micro sleep mode during which at least one receiver component is temporarily switched off is described. The receiver is configured to process sub-frames each having a first sub-frame portion followed by a second sub-frame portion, the first sub-frame portion carrying information indicative of whether or not the second sub-frame portion needs to be decoded. A method implementation of this technique comprises the steps of providing a regular micro sleep mode in which the receiver component is switched off after the first sub-frame portion has been decoded in case the decoding indicates that the second sub-frame portion does not need to be decoded, providing an extended micro sleep mode in which the receiver component is switched off immediately after the first sub-frame portion has been received, evaluating a mode setting criterion, and controlling the receiver to enter the regular micro sleep mode or the extended micro sleep mode depending on the mode setting criterion.

Micro sleep mode control for a receiver

A system for controlling a plurality of electronic components arbitrarily assignable to a plurality of integrated circuits of a mobile communications device is provided. The integrated circuits are capable of processing a radio frequency signal. The system includes a control module configured to allocate a subset of the plurality of electronic components constituting at least one signal path between an integrated circuit of the plurality of integrated circuits and an antenna element of the mobile communications device. The control module is further configured to assign the at least one signal path to the integrated circuit, and to transfer control of at least a part of the subset of the plurality of electronic components constituting the at least one signal path to the integrated circuit.

Method and a system for controlling a plurality of electronic components arbitrarily assignable to a plurality of integrated circuits of a mobile communications device

A communication device () for communicating in accordance with a hybrid automatic repeat request protocol, the communication device () comprising a receiving unit () adapted for receiving a communication message including soft-bit values, the soft-bit values representing reliability information for received verification data verifying proper transmission of the communication message, a storage unit () adapted for storing the soft-bit values, and a storage management unit () adapted for dynamically managing storage of the soft-bit values in the storage unit () so that soft-bit values failing to fulfill at least one relevance criteria are not maintained in the storage unit ().

Dynamic HARQ buffer management

The invention refers to generating a digital signal from an analog signal, wherein the analog signal is amplified according to a gain control value before being converted to a digital value by means of an analog-to-digital converter, wherein a DC offset value of the analog signal is determined, and the gain control value is generated as a function of the dynamic range of the analog-to-digital converter and the DC offset value. The invention further refers to a corresponding circuit and a computer program.

Receiver gain adjustment to reducing an influence of a DC offset

A control entity () for a communication device () and for communicating in accordance with a Digital Radio Frequency interface using a sequence of layers including a physical layer (), a protocol layer () and a programming model layer (), the control entity () comprising an interface control unit () implementing an interface control sub layer of the programming model layer () and adapted for controlling the protocol layer () and the physical layer (), and a configuration interface () communicatively coupled to the interface control unit () and adapted for enabling an operator to configure a timing of control commands for controlling the control entity ().

Control of a digital radio frequency interface

An embodiment of the invention provides a communication device () for processing data samples and comprises a communication entity () and a further communication entity () communicatively coupled to the communication entity () with a digital interface. The communication entity () comprises a timing generation unit () adapted for generating real-time related timing information for operating hardware components of the communication entity () when processing data samples. The further communication entity () is adapted for operating hardware components of the further communication entity () in a sample-driven way when processing data samples.

Communication entity with timing generator coupled via a digital protocol to sample-driven further communication entity

The invention relates to a technique for controlling a synchronization of a terminal device () with a wireless network, e.g. an LTE network, wherein data are transmitted as a continuous data signal on a radio interface () while being processed block-wise in the terminal (). A method embodiment of the technique for achieving at least a downlink () synchronization comprises establishing a time-address mapping (TAM,) indicative of an association of a reference time value of an internal clock () with a reference address in the reception data buffer (); determining an address of data samples representing the received data block in the reception data buffer () based on the time-address mapping; and initiating a block-wise reading of the data block from the reception data buffer () based on the determined address.

Technique for synchronizing a terminal device with a wireless network

A technique for rate matching a bit stream (c(k)) output from a channel encoder () to a data transmission rate on a physical transmission channel is described. A method embodiment of the technique comprises the steps of determining, at a beginning of a transmission time interval for a transmission of one or more code blocks on the transmission channel, bit positions of interleaver padding bits (dummy and/or filler bits) in an output buffer for buffering the output bits before transmission on the physical transmission channel; storing the determined padding bit positions (); and determining, based on the stored padding bit positions, positions (d(k)) of the output bits from the channel encoding stage () in the output buffer, wherein the stored padding bit positions are re-used for each of the one or more code blocks.

Technique for rate matching in a data transmission system

A technique for generating a single carrier frequency division multiple access (SC-FDMA) signal is described, in which from a set of M input symbols a set of N output symbols (M&#x3c;N) is generated. A method implementation of this technique comprises receiving a set of M input symbols in a time domain representation, subjecting the set of M input symbols to an interpolation operation in the time domain to obtain L interpolated samples (L&#x2266;N), mapping the interpolated symbols, or symbols derived from the interpolated symbols, to N orthogonal sub-carriers, and outputting N output symbols in a time domain representation.

Single carrier frequency division multiple access technique

An embodiment of the invention provides a communication device () which comprises a communication entity () and a further communication entity () communicatively coupled to the communication entity () in accordance with a Digital Radio Frequency protocol. The communication entity () comprises a protocol layer (), the further communication entity () comprises a protocol layer (), and the protocol layers () of the communication entity () and of the further communication entity () are connected via a protocol-physical interface () which provides for a parallel bidirectional signal interfacing. The protocol-physical interface () is adapted for selectively connecting the protocol layers () directly or via physical layers ().

Growing community of inventors

Nürnberg, Germany

Steffen Reinhardt