Numascale As

Steffen Persvold

Einar Rustad

Goutam Debnath

Thomas Moen

Helge Simonsen

Thibaut Palfer-Sollier

Kai Arne Midjås

Mario Lodde

The invention relates to a snoop filter device, a node controller, a multicomponent computer system, a computer-implemented method, a data processing system and a computer-readable storage medium aiming at enabling improved tracking of a scalable number of cache elements in multiprocessor systems. The invention involves scaling of a snoop filter device according to the number of cache elements that it is desirable to track.

Snoop filter scalability

The invention relates to a device for use in maintaining cache coherence in a multiprocessor computing system. The snoop filter device is connectable with a plurality of cache elements, where each cache element comprises a number of cache agents. The snoop filter device comprises a plurality of snoop filter storage locations, where each snoop filter storage location is mapped to one cache element.

Snoop filter device

The present invention is related to a digital circuit testing and analysis module system comprising a memory (). The memory () is addressed by numerical values defined by a group of digital signals. A respective memory location associated with a specific numerical value indicates a status of the group of digital signals. The status can for example reflect the validity of the signals in the group of signals when testing a circuit.

Digital circuit testing and analysis module, system and method thereof

A cache coherent node controller at least includes one or more network interface controllers, each network interface controller includes at least one network interface, and at least two coherent interfaces each configured for communication with a microprocessor. A computer system includes one or more of nodes wherein each node is connected to at least one network switch, each node at least includes a cache coherent node controller.

Coherent node controller

A computer system includes a first group of CPU modules operatively coupled to at least one first Programmable ASIC Node Controller configured to execute transactions directly or through a first interconnect switch to at least one second Programmable ASIC Node Controller connected to a second group of CPU modules running a single instance of an operating system.

Programmable cache coherent node controller

The present invention relates to cache coherent node controllers for scale-up shared memory systems. In particular it is disclosed a computer system at least comprising a first group of CPU modules connected to at least one first FPGA Node Controller configured to execute transactions directly or through a first interconnect switch to at least one second FPGA Node Controller connected to a second group of CPU modules running a single instance of an operating system.

Growing community of inventors

Oslo, Norway

Steffen Persvold