Qimonda Ag

Qimonda Flash Gmbh

Steffen Meyer

Rolf Weis

Nicolas Nagel

Michael Specht

Dirk Manger

Detlev Richter

Roman Knoefler

Christoph Kleint

Christoph Noelscher

Klaus Knobloch

Frank Heinrichsdorff

Gert Koebernik

Christoph Friederich

Jan Gutsche

Eike Ruttkowski

Burkhard Ludwig

Joseph Willer

Kenny Oisin

Holger Moeller

Doris Keitel Schulz

Jens Schmidt

The present invention provides an integrated circuit including N1 NAND flash array segments with N2 local bit lines, N1 intra array multiplexers and N2/2 global bit lines. Further, the present invention provides a method of producing an integrated circuit including N1 NAND flash array segments with N2 local bit lines, N1 intra array multiplexers and N2/2 global bit lines.

Method of forming an integrated circuit with NAND flash array segments and intra array multiplexers and corresponding integrated circuit with NAND flash array segments and intra array multiplexers

An integrated circuit including a capacitor and a method of fabricating an integrated circuit. The capacitor has a first electrode. A plurality of conductive lines is separated from each other and is configured to be held at a potential being the same for all conductive lines. A second electrode encloses individual ones of the conductive lines at a top side and at least one lateral side and is separated from the first electrode by a dielectric layer. The second electrode includes a polycrystalline semiconductor material, a metal or a metal-semiconductor compound.

Integrated circuit including a capacitor and method

A method of fabricating an integrated circuit, including the steps of forming a first mask layer in the form of a hard mask layer including a plurality of first openings and a second mask layer with at least one second opening which at least partially overlaps with one of the first openings, wherein the at least one second opening is generated lithographically; and at least two neighboring first openings are distanced from each other with a center to center pitch smaller than the resolution limit of the lithography used for generating the second opening.

Method of fabricating an integrated circuit

Embodiments of the present invention relate generally to integrated circuits, methods for manufacturing an integrated circuit, memory modules, and computing systems.

Integrated circuits; methods for manufacturing an integrated circuit; memory modules; computing systems

An interconnection structure includes two staggered contact rows of evenly spaced contacts. Each contact row extends along a first direction. The interconnection structure further includes conductive lines extending along a second direction that intersects the first direction. The interconnection structure further includes intermediate contacts, where each intermediate contact is in contact with one of the contacts and one of the conductive lines.

Interconnection structure and method of manufacturing the same

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Dresden, Germany

Steffen Meyer