Nexperia B.v.

Nxp B.v.

Steffen Holland

Zhihao Pan

Hans-Martin Ritter

Soenke Habenicht

Stefan Berglund

Jochen Wynants

Tonny Kamphuis

Leo Van Gemert

Hartmut Buenning

Tim Boettcher

Wolfgang Schnitt

Sascha Moeller

Friedrich E Hahn

Thomas Igel-Holtzendorff

Tobias Sprogies

Joachim Utzig

Hans Van Rijckevorsel

Olaf Pfennigstorf

Y Kuang Huang

Uwe Podschus

Ritter Hans-Martin

A semiconductor device () comprising: a doped semiconductor substrate (); an epitaxial layer (), disposed on top of the substrate, the epitaxial layer having a lower concentration of dopant than the substrate; a switching region disposed on top of the epitaxial layer; and a contact diffusion () disposed on top of the epitaxial layer, the contact diffusion having a higher concentration of dopant than the epitaxial layer; wherein the epitaxial layer forms a barrier between the contact diffusion and the substrate.

Semiconductor device

A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface, a backside and side surfaces extending between the major surface and the backside. The semiconductor device also includes at least one metal layer extending across the backside of the substrate. A peripheral part of the at least one metal layer located at the edge of the substrate between the backside and at least one of the side surfaces extends towards a plane containing the major surface. This can prevent burrs located at the peripheral part of the at least one metal layer interfering with the mounting of the backside of the substrate on the surface of a carrier.

Semiconductor device and method of making a semiconductor device

A semiconductor device and method of manufacturing a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a semiconductor layer located on the substrate; at least one shallow trench and at least one deep trench. Each of the at least one shallow trench and the at least one deep trench extending from a first major surface of the semiconductor layer. Sidewall regions and base regions of the trenches comprise a doped trench region and the trenches are at least partially filled with a conductive material contacting the doped region. The shallow trenches terminate in the semiconductor layer and the deep trench terminates in the semiconductor substrate.

Multi-trench semiconductor device and method of manufacture thereof

A semiconductor device and a method of making the same. The device includes a semiconductor substrate provided in a chip-scale package (CSP). The device also includes a plurality of contacts provided on a major surface of the substrate. The device further includes an electrically floating metal layer forming an ohmic contact on a backside of the semiconductor substrate. The device is operable to conduct a current that passes through the substrate from a first of said plurality of contacts to a second of said plurality of contacts via the metal layer on the backside.

A semiconductor device and a method of making the same is provided. The device includes a semiconductor substrate having a major surface and a back surface. The device also includes a bipolar transistor. The bipolar transistor has a collector region located in the semiconductor substrate; a base region located within the collector region and positioned adjacent the major surface; an emitter region located within the base region and positioned adjacent the major surface; and a collector terminal located on the major surface of the semiconductor substrate. The collector terminal includes: a first electrically conductive part electrically connected to the collector region; an electrically resistive part electrically connected to the first electrically conductive part, and a second electrically conductive part for allowing an external electrical connection to be made the collector terminal. The second conductive part is electrically connected to the first conductive part via the resistive part.

Various aspects of the disclosure are directed to circuitry that may be used to shunt current. As may be consistent with one or more embodiments a first circuit has a plurality of alternating p-type and n-type semiconductor regions with respective p-n junctions therebetween, arranged between an anode end and a cathode end. A second (e.g., bypass) circuit is connected to one of the alternating p-type and n-type semiconductor regions, and forms a further p-n junction therewith. The second circuit operates to provide carrier flow, which influences operation of the first circuit.

Carrier bypass for electrostatic discharge

A semiconductor ESD protection device comprising a vertical arrangement of alternating conductivity type layers, wherein the layers are arranged as silicon controlled rectifier and wherein the silicon controlled rectifier is arranged as vertical device and having top and bottom opposing contacts.

ESD protection device

A resistor-equipped transistor includes a package that provides an external collector connection node (), an external emitter connection node () and an external base connection node (). The package contains a substrate upon which a transistor (), first and second resistors, and first and second diodes are formed. The transistor has an internal collector (), an internal emitter () and an internal base () with the first resistor () being electrically connected between the internal base and the external base connection node and the second resistor () being electrically connected between the internal base and the internal emitter. The first and second diodes are electrically connected in series between the external base connection node and the external collector connection node with the first diode () having a first cathode-anode orientation that is opposite of a second cathode-anode orientation corresponding to the second diode ().

Methods, systems and devices for electrostatic discharge protection

Electrostatic discharge (ESD) protection is provided for discharging current between input and output nodes. In accordance with various embodiments, an ESD protection device includes an open-base transistor having an emitter connected to the input node and a collector connected to pass current to the output node via a resistor in response to a voltage at the input node exceeding a threshold that causes the transistor to break down. The resistor is coupled across emitter and collector regions of a second open-base transistor that is configured to turn on for passing current in response to the current across the resistor exceeding a threshold that applies a threshold breakdown voltage across the second transistor. In some implementations, an emitter and/or base of the second transistor are connected to, or are respectively the same region as, a base and a collector of the first transistor.

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Hamburg, Germany

Steffen Holland