USA as Represented by Secretary of the Navy

Stefen Hui

James W Bond

James R Zeidler

David W Stein

William Y Velez

A simplified interference suppressor extends the applicability of adaptive ocally optimum techniques to high speed communication systems. Traditional adaptive locally optimum processing amplitude quantity techniques compel baseband sample amplitudes calculation requiring square root operations that could limit the use of these techniques. The simplified interference suppressor utilizes amplitude squared values of baseband samples while maintaining the performance of those processing algorithms requiring the complexities of baseband sample amplitude calculation.

Simplified interference suppressor

The frequency domain kernel processor of the present invention comprises a cheduler for selecting samples from blocks of Fourier transform coefficients in a predetermined sequence and for outputting the selected samples as serial terms s and as parallel terms u. A transform processor is coupled to the scheduler to receive the terms s and u. The transform processor comprises transform calculators for calculating output values p and f as functions of terms s and u to model the interference and to reveal the desired signal, a first sum calculator for calculating a sum of p values, a second summing calculator for calculating a sum of f values, and a divider for calculating, the quotient of the sum of p values divided by the sum of f values. An output buffer stores the outputs of the divider for formatting as a spectral display.

Frequency domain kernel processor

A frequency domain kernel phase processor comprises an input buffer to st Fourier coefficients input from a Fourier transform of a communications signal. A communications signal suitable for processing by the present invention typically comprises a desired signal masked by a stronger interference signal having varying power that spans a range of frequency bins encompassing the desired signal. A scheduler inputs Fourier transform coefficients from the input buffer and generates a series of magnitude squares and symmetric phase differences for each frequency bin. The magnitude squares and the symmetric phase differences are output to phase transform processors which transform the symmetric phase differences to reveal the desired signal. The transformed outputs from the phase transform processors are output to an output buffer to be formatted and displayed.

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Spring Valley, CA, United States of America

Stefen Hui