Samsung Electronics Co., Ltd.

Stefanovich Genrikh

Eun-hong Lee

Young-soo Park

Choong-rae Cho

Choong-Rae Cho

Chang-jung Kim

I-hun Song

Myoung-jae Lee

Seung-eon Ahn

Sung-Il Cho

In-Kyeong Yoo

Chang-bum Lee

Chang-Wook Moon

Dong-hun Kang

Bo-soo Kang

El Mostafa Bourim

A non-volatile memory device including a variable resistance material is provided. The non-volatile memory device may include a buffer layer, a variable resistance material layer and/or an upper electrode, for example, sequentially formed on a lower electrode. A schottky barrier may be formed on an interface between the buffer layer and the lower electrode. The variable resistance material layer may be formed with a variable resistance property.

Non-volatile memory device including a variable resistance material

Provided are a thin film transistor and a method of manufacturing the same. The thin film transistor may include a gate; a channel layer; a source and a drain, the source and the drain being formed of metal; and a metal oxide layer, the metal oxide layer being formed between the channel layer and the source and the drain. The metal oxide layer may have a gradually changing metal content between the channel layer and the source and the drain.

Thin film transistor having a graded metal oxide layer

Provided are a diode structure and a memory device including the same. The diode structure includes: a first electrode; a p-type Cu oxide layer formed on the first electrode; an n-type InZn oxide layer formed on the p-type Cu oxide layer; and a second electrode formed on the n-type InZn oxide.

Diode structure and memory device including the same

Provided is a variable resistance random access memory device having an n+ interfacial layer and a method of fabricating the same. The variable resistance random access memory device may include a lower electrode, an n+ interfacial layer on the lower electrode, a buffer layer on the n+ interfacial layer, an oxide layer on the buffer layer and having a variable resistance characteristic and an upper electrode on the oxide layer.

Variable resistance random access memory device and a method of fabricating the same

Example embodiments are directed to a junction field effect thin film transistor (JFETFT) including a first electrode formed on a substrate, a first conductive first gate semiconductor pattern formed on the first gate electrode, a second conductive semiconductor channel layer formed on the substrate and the first conductive first gate semiconductor pattern, and source and drain electrodes formed on the second conductive semiconductor pattern and located at both sides of the first conductive gate semiconductor pattern. The JFETFT may further include a first conductive second gate semiconductor pattern formed on a portion of the second conductive semiconductor channel layer between the source electrode and the drain electrode, and a second gate electrode formed on the first conductive second gate semiconductor pattern.

Junction field effect thin film transistor

An electrode structure having at least two oxide layers that more reliably switch and operate without the use of additional devices and a non-volatile memory device having the same are provided. The electrode structure may include a lower electrode, a first oxide layer formed on the lower electrode, a second oxide layer formed on the first oxide layer and an upper electrode formed on the second oxide layer wherein at least one of the first and second oxide layers may be formed of a resistance-varying material. The first oxide layer may be formed of an oxide having a variable oxidation state.

Growing community of inventors

Suwon-si, South Korea

Stefanovich Genrikh