Rambus Inc.

Netlogic Microsystems, Inc

Broadcom Corporation

Cadence Design Systems, Inc.

Other

Highlands Corporation

Nusemi Inc.

Nexlogic Microsystems, Inc.

Stefanos Sidiropoulos

Ely K Tsern

Richard E Perego

Kevin S Donnelly

Bruno Werner Garlepp

Mark A Horowitz

Donald C Stark

Jared L Zerbe

Pak Shing Chau

Craig Edward Hampel

Jun Y Kim

Roxanne T Vu

Leung Yu

Carl William Werner

Tsyr-Chyang Ho

Benedict Chung-Kwong Lau

Marc Loinaz

Frederick Abbott Ware

Billy Wayne Garrett, Jr

Yingxuan Li

Clemenz L Portmann

Richard Maurice Barth

Paul G Davis

Dean Liu

Fredrick A Ware

Scott C Best

Benedict C Lau

Nikhil Acharya

Haw-Jyh Liaw

R Shekhar Narayanaswami

Kun-Yung Chang

Whay Sing Lee

Shahriar Rabii

Halil Cirit

Shwetabh Verma

Parastoo Nikaeen

Athanasios Agamamnon Kasapi

Pradeep Batra

Mehran Mohammadi Izad

Don Stark

Aida Varzaghani

Bardia Bozorgzadeh

R Sekhar Narayanaswami

Joe-Anand Louis-Chandran

An IC chip can include a buffer and correction module that receives a set of multiphase clock signals at a given frequency, the buffer and correction module can include a differential skew detector that detects a skew between signals of the set of multiphase clock signals. The skew detector can include a set of SR latches. Differential clock signals of the set of multiphase clock signals are input into each SR latch, and the differential clock signals of the set of multiphase clock signals are set to be 180 degrees out of phase. A voltage difference between a DC component of a first output signal and a DC component of a second output signal of a respective SR latch in the set of SR latches varies as a function of the skew between the differential clock signals of the set of multiphase clock signals.

Differential clock skew detector

A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

Memory component with pattern register circuitry to provide data patterns for calibration

An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

Flash memory controller with calibrated data communication

An integrated circuit device includes an output driver having a data signal terminal, logic circuitry, and a driver circuit coupled to the logic circuitry and data signal terminal. The driver circuit is configured to drive a signal corresponding to a symbol onto the data signal terminal, wherein the symbol is an N-bit symbol, having one of 2N predefined values, N is an integer greater than 1, and the signal corresponding to the symbol has one of 2N signal levels. The driver circuit includes first, second and third driver sub-circuits, each driven by an input corresponding to one or more bits of the N-bit symbol, wherein the second and third driver sub-circuits are weighted, relative to the first driver sub-circuit, to reduce gds distortion in the signal.

Multi-PAM output driver with distortion compensation

Physical-layer information is conveyed within a packetized communication network via a timing-modulated side channel to yield low-latency physical interface control without consuming host-layer signaling bandwidth. Multi-modal transceivers at opposite ends of a signaling link optionally communicate to confirm mutual support and signaling headroom for timing-modulated information exchange before transitioning from an in-band feedback mode to a side-channel feedback mode.

Timing-modulated side channel

Memory controller that calibrates a transmit timing offset

An integrated circuit device includes a sense amplifier with an input to receive a present signal representing a present bit. The sense amplifier is to produce a decision regarding a logic level of the present bit. The integrated circuit device also includes a circuit to precharge the input of the sense amplifier by applying to the input of the sense amplifier a portion of a previous signal representing a previous bit. The integrated circuit device further includes a latch, coupled to the sense amplifier, to output the logic level.

Multiphase receiver with equalization circuitry

A transceiver integrated circuit (IC) receives signals having a mix of idle characters and data via a multi-lane system-side signaling interface at a first signaling rate compliant with a standards-based signaling protocol. The transceiver IC outputs signals via a multi-lane line-side signaling interface at a second signaling rate that is lower than the first signaling rate and non-compliant with the standards-based signaling protocol and also outputs one or more requests to a remote IC source of the signals received via the system-side signaling interface to adjust a proportion of idle characters within the received signals as necessary to balance a data rate of the received signals with the second signaling rate without adjusting the first signaling rate.

Adaptable rate transceiver

Memory system with calibrated data communication

A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration.

Growing community of inventors

Palo Alto, CA, United States of America

Stefanos Sidiropoulos