Stmicroelectronics S.r.l.

Micron Technology Incorporated

Other

Sgs-thomson Microelectronics S.r.l.

Hynix Semiconductor Inc.

Sgs-italy Microelectronics S.r.l.

Stefano Zanardi

Domenico Monteleone

Graziano Mirichigni

Luca Porzio

Erminio Di Martino

Giacomo Bernardi

Maurizio Branchetti

Giovanni Campardo

Jacopo Mulatti

Carla Maria Golla

Chee Weng Tan

Andre Klindworth

Andrea Ghilardelli

Massimiliano Picca

Matteo Zammattio

Giulio Martinozzi

Sebastien Lemarie

Osama Khouri

Stefano Ghezzi

Marcello Carrera

Rino Micheloni

Massimo Iaculo

Roberto Ravasio

Carla Maris Golla

Angelo Della Monica

Giovanni Guerra

Armando Conci

Sebastien LeMarie

Apparatuses and methods for commands to perform wear leveling operations are described herein. An example apparatus may include a memory configured to receive a wear leveling command and to perform a wear leveling operation responsive to the wear leveling command. The memory may further be configured to recommend a wear leveling command be provided to the memory responsive to a global write count exceeding a threshold. The global write count may be indicative of a number of write operations performed by the memory since the memory performed a wear leveling operation.

Performing wear leveling operations in a memory based on block cycles and use of spare blocks

Apparatuses and methods for providing data to a configurable storage area are described herein. An example apparatus may include an extended address register including a plurality of configuration bits indicative of an offset and a size, an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits, and a buffer configured to store data, the data including data intended to be stored in the storage area. A memory control unit may be coupled to the buffer and configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command.

Apparatuses and methods for providing data to a configurable storage area

Apparatuses and methods for performing write count threshold wear leveling operations

Apparatuses and methods for providing data to a configurable storage area are disclosed herein. An example apparatus may include an extended address register including a plurality of configuration bits indicative of an offset and a size, an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits, and a buffer configured to store data, the data including data intended to be stored in the storage area. A memory control unit may be coupled to the buffer and configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command.

Apparatuses and methods for providing data from a buffer are disclosed herein. An example apparatus may include an array, a buffer, and a memory control unit. The buffer may be coupled to the array and configured to store data. The memory control unit may be coupled to the array and the buffer. The memory control unit may be configured to cause the buffer to store the data responsive, at least in part, to a first write command and may further be configured to cause the buffer to store the data in the array responsive, at least in part, to a flush command. The memory control unit may further be configured to interrupt the flush command to prepare for a read command or a second write command and resume the flush command once the read command or the second write command is performed.

Apparatuses and methods for providing data from a buffer

Apparatuses and methods for providing data from a buffer are disclosed herein. An example apparatus may include an array, a buffer, and a memory control unit. The buffer may be coupled to the array and configured to store data. The data may include data intended to be stored in the storage area. The memory control unit may be coupled to the array and the buffer. The memory control unit may be configured to cause the buffer to store the data responsive, at least in part, to a write command and may further be configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command.

Subject matter disclosed herein relates to an erasable memory device, and more particularly to a securely erasable flash memory device.

Secure memory device erase

An electrically programmable memory including: an array of a plurality of memory cells arranged accordingly to a NAND architecture, said memory cells grouped into a plurality of memory blocks and each memory block including a plurality of memory pages; means for receiving an address corresponding to a respective memory block; selecting means for selecting the addressed memory block; and means for detecting a failure of the addressed memory block, wherein the means for detecting a failure includes: a plurality of registers, each register corresponding to a respective memory block and storing an indication of the failure of the respective memory block; and means for reading the register corresponding to the addressed memory block in response to the receiving of the address, and wherein the programmable memory further includes at least one redundant memory block of memory cells including a plurality of redundant memory pages, the selecting means selecting the at least one redundant memory block in place of the addressed memory block in response to the reading of the indication of the failure.

Programmable NAND memory

A page buffer for an electrically programmable memory includes a plurality of storage units, each comprising a first latch and a second latch. Input switching means loads into the latch the data bit to be written and to be temporarily stored. The input switching means has an input terminal connected to the respective data line for receiving a set voltage provided therethrough. The input switching means provides the set voltage to the first or second input/output terminals of the latch depending on the data bit to be written. An output switch device transfers onto the respective data line the read data bit temporarily stored into the latch and has a first terminal coupled to one among the first and second input/output terminals of the latch, a second terminal connected to the respective data line and a control terminal receiving the output control signal.

Page buffer circuit and method for a programmable memory device

A method is provided for transferring data in a memory that includes memory cells forming memory pages, and a page buffer that includes a register, with signal lines selectively transferring data stored in the register to the memory cells of a selected one of the memory pages and an output interface of the memory. Data read from or to be written to the memory cells of the selected one of the memory pages is at least temporarily stored in the register, and outputs of the register are buffered so as to decouple the outputs of the register from the signal lines. The signal lines include bitlines that are each coupled to some of the memory cells and data lines that are coupled to the output interface of the memory. The buffering comprises selectively driving the bitlines or the data lines according to a data word that is stored in the register.

Method of transferring data in an electrically programmable memory

A page buffer is provided for an electrically programmable memory that includes multiple memory cells forming multiple memory pages. The page buffer includes a register for at least temporarily storing data read from or to be written to the memory cells of a selected memory page. The register includes multiple latches and multiple buffer elements. Each of the latches is coupled to at least one signal line for transferring the data bit that is stored in the latch. Each of the buffer elements decouples an output of a corresponding one of the latches from the signal line, with the buffer element driving the signal line according to the data bit stored in the corresponding latch. Also provided is a method of transferring data from a register to signal lines in an electrically programmable memory.

Page buffer for a programmable memory device

An electrically programmable memory device is proposed including: a matrix of memory cells arranged in a plurality of memory arrays and at least one redundancy array; and a substituting structure that substitutes the use of each memory array with the use of one of the at least one redundancy array in response to a failure of the memory array, wherein the memory arrays are grouped into at least one set. The substituting structure includes: a structure for associating each set with a predetermined one of the at least one redundancy array; a flag for each memory array indicative of the failure of the memory array; and a selecting for enabling each memory array or the associated redundancy array according to the corresponding flag.

Programmable memory device with an improved redundancy structure

A method for error control in multilevel memory cells storing a configurable number of bits. The error control is performed using an error-control code which operates, in the encoding phase, on b-bit binary strings made up of k symbols of r-bit data. When the memory cells store a number r of bits, a data symbol is formed only with the data bits stored in a memory cell. When the memory cells store a number s of bits smaller than r, a data symbol is formed with the data bits stored in a memory cell and with r-s bits having a pre-determined logic value, in which the data bits stored in the memory cell are arranged in the least significant part of the data symbol, and the r-s bits having a pre-determined logic value are arranged in the most significant part of the data symbol.

Growing community of inventors

Seriate, Italy

Stefano Zanardi