Ferroelectric Memory Gmbh

Ferrorelectric Memory Gmbh

Stefano Sivero

Alessandro Palludo

Corrado Villa

Stefan Müller

Rashid Iqbal

Fabio Tassan Caser

Duc Le Minh

Disclosed herein are devices, methods, and systems for calibrating a sensing capacitance value used by a sensing circuit when reading memory cells of a memory. The calibration circuit includes a calibration cell associated with a predefined programming state of the calibration cell. The calibration circuit also includes a read circuit configured to perform a read operation on the calibration cell that generates a calibration voltage based on the predefined programming state and convert the calibration voltage to a target capacitance value based on the calibration voltage. The read circuit is configured to provide the target capacitance value to the memory as the sensing capacitance for the sensing circuit to use when reading the memory cells of the memory.

Devices, methods, and systems for calibrating a sensing capacitor used in a sensing circuit for reading memory cells

Disclosed herein are devices, methods, and systems for operating a sense amplifier comprising a plurality of transistors connected in a cascode configuration. The plurality of transistors are configured to sense, in a read operation mode, a switching signal from the state-programmable memory element, and to apply, in a write operation mode, a programming voltage level to the state-programmable memory element. The plurality of transistors are configured to receive a supply voltage at, in the read operation mode, a first supply voltage level that is lower than the programming voltage level and at, in the write operation mode, the programming voltage level, and to operate the sense amplifier in the read operation mode and the write operation mode with no more than a maximum operational voltage level across each of the plurality of transistors that is less than the programming voltage level.

Low-voltage sense amplifier for reading a state-programmable memory element

Various aspects relate to a multiply and accumulate circuit, the multiply and accumulate circuit including: a plurality of multiply operation cells configured in a matrix arrangement. A respective multiply operation cell of the multiply operation cells includes: a field-effect transistor and a programmable switch in a series connection, wherein the field-effect transistor and the programmable switch are configured to control a current flow through the respective multiply operation cell to realize a multiplication operation. The multiply operation cells of a set of the plurality of multiply operation cells share a corresponding control line to realize an accumulation operation in addition to the multiply operations carried out by the set of multiply operation cells.

Multiply operation circuit, multiply and accumulate circuit, and methods thereof

Disclosed herein are devices, methods, and systems for reading/writing memory cells of a memory, where the memory cells includes a memory element that is writable to at least three different remanent polarization states. A sensing circuit determines, in a read operation, a stored state of the memory element from among the at least three different remanent polarization states based on a sensed change in a remanent polarization of the memory element caused by an applied read voltage. A biasing circuit applies, in a write operation, apply a bias voltage level across the memory element to (re)write the memory element to the stored state.

Devices, methods, and systems for a multilevel memory cell

Disclosed herein is a memory arrangement and method thereof for locally marking bad memory cells. The memory arrangement includes a group of memory cells and a driver circuit for operating the group of memory cells. The driver circuit includes a remanent-polarizable memory element (e.g., a remanent-polarizable field-effect transistor). Depending on a memory state of the remanent-polarizable memory element, the driver circuit enables or disables the operation (e.g., a read/write operation) on the group of memory cells.

Locally embedded bad sector marking for a memory

Disclosed herein is an adaptive voltage regulator that includes a voltage regulator circuit configured to provide a regulated output voltage at an output node of the adaptive voltage regulator circuit. The adaptive voltage regulator also includes an adaptation circuit coupled to the output node that is configured to adapt a charging characteristic associated with a charging of the output node to a predefined output voltage as a function of a load coupled to the output node. The adaption circuit may be configured to selectively provide additional charging current that charges the output node to the predefined output voltage depending on the load.

Regulator circuit and methods thereof

Various aspects relate to a memory cell including: a field-effect transistor memory structure, wherein a source/drain current through the field-effect transistor memory structure is a function of a gate voltage supplied to a gate of the field-effect transistor memory structure and a memory state in which the field-effect transistor memory structure is residing in; and an access device coupled to the gate of the field-effect transistor memory structure, wherein the access device is configured to control a voltage present at the gate of the field-effect transistor memory structure.

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Comun Nuovo, Italy

Stefano Sivero