Stmicroelectronics S.r.l.

Stefano Pucillo

Claudio Mucci

Valentina Nardone

Roberto Antonio Canegallo

Luca Perugini

Luca Ciccarelli

Fabio Campi

Massimiliano Innocenti

A method is for designing an accelerator for digital signal processing including defining a software programmable fully pre-laid out macro by pre-laying out with a fixed topology a control logic of the DSP accelerator to obtain a fully pre-laid out control logic. The method further includes defining a hardware programmable partially pre-laid out macro by customizing a configurable layout area, thereby mapping a computational logic based on computation kernels related to an application of the DSP accelerator. A partially pre-laid out computational logic is therefore obtained.

Method of designing a high performance application specific integrated circuit accelerator

A memory base cell stores a bit of information implemented from a regular and compact structure made up of multiple identical and replicated base elements, on the 'sea of gates' model, in which the base element of the structure is a cell able to be configured with a minimum width in relation to the particular technology used. Such a cell includes a bistable element with an input node operatively connected to a writing data line of the memory base cell, and an output node operatively connected to a reading data line of the memory base cell. The bistable element also has a first inverter and a second inverter arranged in a feedback configuration with respect to one another between the input node and the output node of the bistable element.

Memory base cell and memory bank

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Robbiate, Italy

Stefano Pucillo