Freescale Semiconductor,inc.

Nxp Usa, Inc.

Nxp B.v.

Stmicroelectronics S.r.l.

Stmicroelectronics Gmbh

Stefano Pietri

Chris C Dao

Alfredo Olmos

Juxiang Ren

James Robert Feddeler

Michael Todd Berens

Andre Luis Vilas Boas

Ricardo Pureza Coimbra

Yizhong Zhang

Anis Mahmoud Jarrar

Steven K Watkins

Jie Jin

Miten H Nagda

Kumar Abhishek

Olivier Trescases

Hendrik Johannes Bergveld

Jitendra Prabhakar Harshey

Yikun Mo

Ashutosh Jain

Jiawei Fu

V Srinivasan

Jefferson Daniel De Barros Soldera

Juan Camilo Monsalve

Edevaldo Pereira Da Silva Junior

Marcos Augusto De Goes

Luciana Bulgarelli Carvalho

Luis Francisco P Junqueira De Andrade

John M Pigott

Michael A Stockinger

James B Eifert

Ray Charles Marshall

Sunny Gupta

Charles Eric Seaberg

Thomas Henry Luedeke

Dale John McQuirk

David Russell Tipple

Mike Robert Garrard

Garima Sharda

Ivan Carlos Ribeiro Do Nascimento

Jianzhou Wu

Jehoda Refaeli

Wenzhong Zhang

Eduardo Ribeiro Da Silva

Jurgen Geerlings

Felipe Ricardo Clayton

Robert Matthew Mertens

Robert Scott Ruth

Simon Gallimore

Nicolas Grossier

Ateet Omer

Javier Mauricio Olarte Gonzalez

Jader Alves De Lima Filho

Hongyan Yao

Vitor Moreira Gomes

Benjamin J Ehlers

Nidhi Chaudhry

Joel Ray Knight

Sheng Wei Lin

James M Giandelone

Garrin S Felber

Nicolas Grosssier

Oscar Igor Robles Palacios

Jaideep Banerjee

Roberto Angelo Bertoli

A self-calibrating digital-to-analog converter (DAC) is disclosed. The self-calibrating DAC includes a DAC including a least significant bit (LSB) side resistor network and a most significant bit (MSB) side resistor network. At least the MSB side resistor network includes a plurality of trimmable resistors. A resistance to frequency converter coupled with an output of the DAC is included to generate a frequency fbased on a value of the LSB side resistor network or the MSB side resistor network. A monitor is included to generate a counter value by comparing fwith a high frequency clock having a constant frequency f. A memory is included to store at least two counter values generating by comparing fand fonce when the LSB side resistor network is connected while the MSB side resistor network is floating and once when the LSB side resistor network is floating while only one of the resistors in the MSB side resistor network is connected and all other resistors in the MSB side resistor network are floating. A comparator is included to compare the at least two counter values. A trimming controller is included to generate a trimming signal to trim one of the plurality of trimmable resistors based on an output of the comparator.

Self calibrating digital-to-analog converter

A digital to analog converter (DAC) includes an amplifier including a buffer of the DAC, and a resistor ladder arrangement coupled to a non-inverting input terminal of the amplifier to generate a voltage based on a digital control word. The arrangement includes a first, least-significant bit, segment arranged in one of an R-2R or unit-R configuration, a second, most-significant bit, segment including one or more units each including a second-segment-resistor having a resistor terminal coupled to a respective second switch and having a second resistance, R, and a third segment including one or more third-segment-resistors coupled in parallel to the non-inverting input terminal and connected to a first reference voltage terminal. M2 designates a number of bits in the digital control word for controlling the second switches, and the third segment has a total resistance, Rsp, based on M2.

Digital to analog converter

A bias current generator circuit includes a current path and a leakage control circuit. The current path is connected between a supply voltage and a ground level. The current path includes a transistor and a resistor. The transistor has a current channel connected in the current path. The resistor has an upper terminal and a lower terminal connected in the current path, and a well contact to allow a reverse leakage current of the resistor to flow through. The leakage control circuit is connected to the supply voltage. The leakage control circuit includes a driving transistor to provide a driving voltage to the well contact of the resistor, and to allow the reverse leakage current of the resistor to flow into the leakage control circuit.

Bias current generator circuit

A bandgap reference correction circuit comprising a bandgap reference circuit comprising a first resistor; a first oscillator comprising a second resistor, wherein a frequency of a first oscillator output signal of the first oscillator depends on a resistance of the second resistor; and a compensation module configured to: receive the first oscillator output signal from the first oscillator and a reference frequency signal from a reference oscillator; determine the frequency of the first oscillator output signal using the reference frequency signal; and set a resistance of the first resistor based on the frequency of the first oscillator output signal.

Bandgap reference compensation circuit

During a sampling phase, an analog front end circuit connects input of a first sampling capacitor to an analog input signal and input of a second sampling capacitor to a reference signal, and connects first and second hold capacitors to ground. During a partial tracking phase, input of the first sampling capacitor is connected to the reference voltage and the input of the second sampling capacitor is connected to the analog input signal. The first hold capacitor is connected to a first output of a gain amplifier and the second hold capacitor to a second output of the gain amplifier. Output of the first sampling capacitor is coupled to a first input of an amplifier and output of the second sampling capacitor is coupled to a second input of the amplifier.

Analog front-end circuit capable of use in a sensor system

A first switch is operable to couple a start-up oscillator circuit to a first crystal pin during operation in a start-up mode and decouple the start-up oscillator circuit from the first crystal pin during operation in a normal mode, and a second switch is operable to couple the start-up oscillator circuit to a second crystal pin during operation in the start-up mode and decouple the start-up oscillator circuit from the second crystal pin during operation in the normal mode. A switched oscillator circuit is coupled to the startup oscillator during operation in the startup mode, and to the first and second crystal pins during operation in the start-up and normal modes. The switched oscillator circuit includes a sample and charge circuit which is configured to sample a direct current (DC) level of the first crystal pin and pre-charge a first coupling capacitor during operation in the startup mode.

Crystal oscillator circuit and method of operation

A clock generation circuit includes a switched capacitor circuit for providing a discrete amount of charge to a resonator for sustaining energization of the resonator at specific portions of the clock cycle.

Clock generation

A low power crystal oscillator is provided. The crystal oscillator includes a gain control stage, a filter stage, and an output stage. The gain control stage includes an input coupled at a first oscillator terminal configured and arranged for connection to a first terminal of a crystal. The filter stage includes an input coupled to an output of the gain control stage. The output stage includes a first transistor having a first current electrode coupled at a second oscillator terminal configured and arranged for connection to a second terminal of the crystal and a control electrode coupled to receive a voltage signal at the first oscillator terminal and a first bias voltage.

Low power crystal oscillator

A digital to analog converter (DAC) that receives a binary coded signal and generates an analog output signal includes a binary-to-thermometer decoder and a resistive network. The decoder receives the binary coded signal, and decodes it into thermometer signals. The resistive network has branches that are coupled to an output terminal of the DAC in response to the thermometer signals. Each of the branches includes first and second resistors, and a switch. The first resistor is coupled between a first reference voltage and the switch, and the second resistor is coupled between a second reference voltage and the switch. The switch couples either the first resistor or the second resistor to the output terminal in response to a corresponding thermometer signal.

Segmented resistive digital to analog converter

A DC-DC converter selectively operates in at least a first burst mode having at least one first-mode charge cycle with a first-mode charging phase followed by a first-mode discharging phase or a second burst mode having at least one second-mode charge cycle with a second-mode charging phase followed by a second-mode discharging phase. A first-mode charging phase is terminated when an inductor current flowing through the inductance reaches a first-mode peak-current threshold, and a first-mode discharging phase is terminated when the inductor current reaches a first-mode valley-current threshold. A second-mode charging phase is terminated when the inductor current reaches a second-mode peak-current threshold, wherein the second-mode peak-current threshold is different from the first-mode peak-current threshold, and the second-mode discharging phase is terminated when the inductor current reaches a second-mode valley-current threshold, wherein the second-mode valley-current threshold is different from the first-mode valley-current threshold.

Charge-cycle control for burst-mode DC-DC converters

A digital to analog converter receives a digital input consisting of first least significant bits, second most significant bits, and third middle significant bits. The digital to analog converter includes first, second, and third sub-DACs. The first sub-DAC receives the first least significant bits, and includes first resistors each contributing a respective voltage, to provide a first output. The second sub-DAC receives the second most significant bits, and includes second resistors each contributing a respective voltage, to provide a second output as an output of the digital to analog converter. The third sub-DAC is connected to the first sub-DAC to receive the first output, and receives the third middle significant bits, and includes third resistors each contributing a respective voltage, to provide a third output to the second sub-DAC. The first and third resistors each has a physical area less than an area of each second resistor.

Segmented digital to analog converter

A circuit includes a high voltage (HV) transistor having a first current electrode, a second current electrode, and a control electrode coupled to receive a control signal. The HV transistor is configured and arranged to be non-conductive when the control signal is at a first state and conductive when the control signal is at a second state. A low voltage (LV) transistor is coupled to the first current electrode of the HV transistor. An HV pad is coupled to the second current electrode of the HV transistor. An operating voltage rating of the HV pad exceeds an operating voltage rating of the LV transistor. A secondary electrostatic discharge protection device is coupled between the second current electrode of the HV transistor and a voltage supply terminal.

High voltage interface circuit

Embodiments provide forced-burst voltage regulation for burst mode direct-current-to-direct-current (DC-DC) converters in integrated circuits. The DC-DC converter generates an output voltage and operates in a burst mode to raise the output voltage to a threshold voltage. A controller is coupled to the DC-DC converter. In operation, the DC-DC converter is configured to perform the burst mode based upon a low-voltage detection for the output voltage. The DC-DC converter is further configured to perform the burst mode when a force-burst command is asserted by the controller to the DC-DC converter regardless of a state for the low-voltage detection. For one embodiment, the force-burst command is asserted as a burst control signal from the controller to the DC-DC converter to generate a long quiet period for sensitive actions. For another embodiment, the force-burst command is asserted using enable and refresh control signals to facilitate low-power operation.

Forced-burst voltage regulation for burst-mode DC-DC converters

A method of powering up a circuit includes powering up a latch circuit in a known latch state by applying a first power supply voltage differential of a first voltage domain across power supply terminals of the latch circuit. A current diode inhibits current diode in a current path between a latch node of the latch circuit and a power supply terminal when the power supply voltage differential is below a threshold voltage during the powering up in which the inhibiting prevents the latch circuit from switching from the known latch state during the powering up.

Power on reset latch circuit

A first voltage scaling power switch is coupled to a first power supply terminal for providing power to a first circuit portion, and a second voltage scaling power switch is coupled between the first power supply terminal providing power to a second circuit portion. A common power rail is coupled the first and second power input nodes during respective voltage scaling modes of the first and second circuit portions. A feedback circuit coupled to the common power rail provides a feedback signal to a control input of the first voltage scaling power switch to regulate a voltage provided by the first power switch, and to a control input of the second voltage scaling power switch to regulate a voltage provided by the second voltage scaling power switch.

Circuit with multiple voltage scaling power switches

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Austin, TX, United States of America

Stefano Pietri