Micron Technology Incorporated

Stefano Perugini

Marco-Domenico Tiburzi

Tommaso Vali

Giulio Giuseppe Marotta

Agostino Macerola

Alessandro Torsi

Carlo Musilli

Agostino Marcerola

Charge pumps of integrated circuit devices might include an input configured to receive an internally-generated first voltage level, an output, and a plurality of stages between its input and output. A particular stage might include a voltage isolation device, a voltage driver, and a capacitance having a first electrode connected to an output of the voltage driver and a second electrode connected to the voltage isolation device. The voltage driver might be responsive to a clock signal and to a voltage level of the output of the voltage driver to selectively connect the output of the voltage driver to either a first voltage node configured to receive the first voltage level, a second voltage node configured to receive a second voltage level lower than the first voltage level, or a third voltage node configured to receive a third voltage level lower than the second voltage level.

Voltage generation circuits

Methods of operating a voltage generation circuit include applying a clock signal to an input of a voltage driver of a stage of the voltage generation circuit, connecting the output of the voltage driver to a first voltage node configured to receive a first voltage when the clock signal has a particular logic level and a voltage level of an output of the voltage driver is less than a threshold, connecting the output of the voltage driver to a second voltage node configured to receive a second voltage, greater than the first voltage, when the clock signal has the particular logic level and the voltage level of the output of the voltage driver is greater than the threshold, and connecting the output of the voltage driver to a third voltage node configured to receive a third voltage, less than the first voltage, when the clock signal has a different logic level.

Methods of operating voltage generation circuits

Voltage generation circuits include a stage including a voltage driver having inputs connected to respective voltage nodes and a clock signal, and a stage capacitance having a first electrode connected to an output of the voltage driver and a second electrode connected to a voltage isolation device. The voltage driver might be configured to connect its output to receive a first voltage when the clock signal has a particular logic level and a voltage level of its output is less than a threshold, to connect its output to receive a second voltage greater than the first voltage when the clock signal has the particular logic level and the voltage level of its output is greater than the threshold, and to connect its output to receive a third voltage less than the first voltage when the clock signal has a different logic level.

Methods of operating a voltage generation circuit, and apparatus configured to perform such methods, include applying a clock signal to an input of a voltage driver of a stage of the voltage generation circuit, connecting the voltage driver output to a first voltage node configured to receive a first voltage when the clock signal has a particular logic level and a voltage level of the voltage driver output is less than a threshold, connecting the voltage driver output to a second voltage node configured to receive a second voltage greater than the first voltage when the clock signal has the particular logic level and the voltage level of the voltage driver output is greater than the threshold, and connecting the voltage driver output to a third voltage node configured to receive a third voltage less than the first voltage when the clock signal has a different logic level.

Methods and apparatus for generation of voltages

Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit. Each switch circuit uses a group of series coupled transistors with a parallel control transistor where the number of transistors in each group may be determined by an expected switch input voltage and a maximum allowable voltage drop for each transistor. A voltage of a particular state of an enable signal is shifted up to the switch input voltage by the level shift circuits. The particular state of the enable signal turns on the voltage switch such that the switch output voltage is substantially equal to the switch input voltage.

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Stefano Perugini