Intel Corporation

Stefano Giaconi

Mingming Xu

Kevin Chang

Wei Wei Wang

Giacomo Rinaldi

The present invention provides GPA embodiments. In some embodiments, a GPA stage with a negative capacitance unit is provided.

High speed receivers circuits and methods

Some embodiments include apparatuses and methods having a receiver unit included in a die and a measurement unit included in the die. The receiver unit includes a sampler to sample a first signal based on timing of a first clock signal to generate a second signal. The measurement unit is arranged to sample the first signal based on timing of a second clock signal to provide information for generation of a graph presenting an eye scan of the first signal. The second clock signal has a frequency asynchronous with a frequency of the first clock signal.

Asynchronous on-die eye scope

Described are phase adjustment circuits for clock and data recovery circuits (CDRs). Systems and apparatuses may include an input to receive a serial data signal, an edge data tap to sample transition edges in the serial data signal for generating a data edge detection signal, a CDR circuit including a phase detector to receive the serial data signal and the data edge detection signal, and to output a phase lead/lag signal indicating the phase difference between the serial data signal and the data edge detection signal, and a phase adjustment circuit to generate phase lead/lag adjustment data. The CDR circuit is to output a recovered clock signal based, at least in part, on the phase lead/lag signal adjusted by the phase lead/lag adjustment data.

Phase adjustment circuit for clock and data recovery circuit

A transmitter, such as a voltage mode driver (VMD)-based push-pull source-series terminated (SST) transmitter, is provided that can consume less current as the amplitude of a voltage output is decreased. The transmitter includes a transmitter circuit having a first branch and a second branch. While the first branch is activated to send an analog output signal, the second branch is deactivated, and vice versa. One or more bit values of an input binary signal can be used to selectively activate and deactivate the first and second branches.

Push-pull source-series terminated transmitter apparatus and method

Described is an apparatus which comprises: a current steering digital-to-analog converter (DAC) to receive a digital bus to control current steering; a switch capacitor network to integrate currents from the DAC, the switch capacitor network having switches which are controllable by a plurality of digital clock signals; an output stage to compare the integrated currents against at least two threshold voltages and to generate an output signal; and a duty cycle corrector (DCC) operable to adjust the at least two threshold voltages to modify duty cycle of the output signal.

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Phoenix, AZ, United States of America

Stefano Giaconi