Stmicroelectronics S.r.l.

Sgs-thomson Microelectronics S.r.l.

Other

Sgs-thomas Microelectronics S.r.l.

Stefano Ghezzi

Giovanni Campardo

Marco MacCarrone

Maurizio Branchetti

Andrea Ghilardelli

Donato Ferrario

Stefano Zanardi

Giuseppe Giannini

Rino Micheloni

Carla Maria Golla

Jacopo Mulatti

Stefano Commodaro

Matteo Zammattio

Guido Lomazzi

Marco Roveda

Irene Babudri

Emilio Yero

Ruggero DeLuca

Davide Villa

Romina Zonca

Piero Enrico Torricelli

Stefano Saltutti

Luigi Costanzo

A removable storage device includes a substrate whereon a plurality of components are arranged. Advantageously, the removable storage device comprises a casing of the package type suitable to completely cover these components and to form, together with the substrate, an external coating of the removable storage device. Moreover, a method is described for assembling at least one removable storage device thus realized.

Removable data storage device and related assembling method

A memory, particularly but not limitatively a flash memory, comprises at least one data storage area comprising a plurality of data storage locations, and an access circuitry for accessing the data storage locations for either retrieving or altering a data content thereof, depending for example on a memory user request. The memory includes at least one first user-configurable flag element and a second user-configurable flag element. Both the at least one first and the second flag elements are used by a user to set a protected state of the respective data storage area against alteration of the content of the data storage locations thereof. The protected state defined by setting the first flag element is user-removable, i.e., it can be removed by request from the user, so as to enable again the alteration of the content of the data storage area. On the contrary, the protected state defined by setting the second flag element is permanent and, once set, it cannot be removed: the data storage area becomes unalterable.

Semiconductor memory with access protection scheme

A MOS capacitor comprises a semiconductor substrate, a first well region of a first conductivity type formed in the substrate, at least one doped region formed in the first well region, and an insulated gate layer insulatively disposed over a surface of the first well region. The at least one doped region and the insulated gate layer respectively form a first and a second electrode of the capacitor. The first well region is electrically connected to the at least one doped region to be at a same electrical potential of the first terminal of the capacitor.

MOS capacitor with wide voltage and frequency operating ranges

A programmable logic array (PLA) includes at least one AND plane including an array of transistors arranged in rows and columns. The transistors belonging to a same column may be connected in series with each other. Two end conduction terminals of the series connected transistors may be coupled to a supply voltage rail and to a reference, respectively. The transistors of the first and last rows of the array may have their control terminals coupled to respective opposite enabling/disabling potentials. Except for the first and last rows, first, second, and third control lines are associated with each row of the array. Except for the first and last rows, each transistor of each row may have its control terminal connected to one of the three control lines associated with its row. The PLA may alternatively include at least one OR plane.

Programmable logic arrays

A biasing device for biasing a memory cell having a substrate bias terminal associated therewith. The biasing device includes a first sub-threshold circuitry block adapted to supply an appropriate current during the device standby phase through a restore transistor connected between a supply voltage reference and the substrate bias terminal of the memory cell, and having a control terminal connected to a bias circuit, in turn connected between the supply voltage reference and a ground voltage reference to drive the restore transistor with a current of limited value. The device further includes a second feedback block for fast charging the substrate bias terminal, being connected between the supply voltage reference and the ground voltage reference and comprising a first bias transistor having a control terminal connected to the ground voltage reference via a stabilization transistor, having in turn a control terminal connected to an output node, and to the control terminal of a first regulation transistor connected between the supply voltage reference and the ground voltage reference, the stabilization transistor and first regulation transistor providing feedback for the bias transistor, thereby to restrict the voltage range of the output node.

Memory cell integrated structure with corresponding biasing device

A method of protecting data in a semiconductor electronic memory, which includes using a protected memory portion within the matrix and respective dedicated decoding portions for storing, into the protected portion, a protection code without the address area of the matrix. The protection code can only be written and/or read through a command interpreter.

Data protection method for a semiconductor memory and corresponding protected memory device

An electronic counter for a semconductor-integrated non-volatile memory device includes a single count cell connected with its output to at least one storage element The count cell comprises a summing block of the half-adder type and a master portion of a master/slave flip-flop of which said storage element is a slave portion. Advantageously, the master portion has an output connected to the input side of a number n of slave registers arranged in parallel.

Electronic counter for a non-volatile memory device integrated on a semiconductor

A charge pump comprises a plurality of stages connected in series, an input terminal of the charge pump being connected to a voltage supply and an output terminal of the charge pump providing an output voltage higher than the voltage supply. Each stage comprises unidirectional current flow MOS transistor means connected between a stage input terminal and a stage output terminal allowing current to flow only from said stage input terminal to said stage output terminal, and a first capacitor with one plate connected to said stage output terminal and another plate driven by a respective first digital signal periodically switching between ground and said voltage supply. The unidirectional current flow MOS transistor means of the stages have independent bulk electrodes, and a bias voltage generator circuit is provided for biasing the bulk electrodes of said unidirectional current flow MOS transistor means at respective bulk potentials which become progressively higher going from the stages proximate to said input terminal to the stages proximate to said output terminal of the charge pump.

Positive charge pump

A row decoding circuit for an electronic memory cell device, particularly in low supply voltage applications, is described. The row decoding circuit is adapted to boost, through at least one boost capacitor, a read voltage to be applied to a memory column containing a memory cell to be read. The circuit is powered between a first supply voltage reference and a second ground potential reference, and comprises a hierarchic structure of cascade connected inverters and a circuit means of progressively raising the read voltage level dynamically. First means are provided for raising the read voltage level to a value equal to the supply voltage plus a threshold voltage, and second means are provided for raising the read voltage level to a value equal to the supply voltage plus twice said threshold voltage.

Row decoder circuit for an electronic memory device, particularly for

Switching circuit that receives a supply voltage, a reference voltage, a line adapted to carry a negative voltage and a control signal, the switching circuit capable of providing at an output a voltage alternatively equal to the reference voltage or to the voltage of the line in response to the control signal. The circuit includes a first MOSFET with a first electrode operationally connected to the line, a second electrode operationally connected to the output, and a control electrode, a second MOSFET with a first electrode operationally connected to the reference voltage, a second electrode operationally connected to the output, and a control electrode, and driving circuitry adapted to bring the control electrodes of the first and second MOSFETs respectively to the supply voltage and to the voltage of the line or, alternatively, to the voltage of the line and to the supply voltage, in response to the control signal.

Switching circuit having an output voltage varying between a reference

The present invention relates to an electronic power on reset circuit of the type including a comparator having at least two inputs and one output for receiving a first reference signal from a generator block and a second signal proportional to a supply voltage from a divider block and for producing an output initialization signal. Advantageously the output is connected to a third turn off enablement input of the comparator through the series of an inverter pair. The generator block and the divider block also include respective turn off enablement inputs connected downstream of the inverter pair.

Power on reset circuit with auto turn off

An integrated device having an N-type well region formed in a P-type substrate and an N.sup.+ type contact ring housed in the well region. The well region forms respective capacitors with a conductive layer superimposed on the substrate, and with the substrate itself. The conductive layer and the substrate are grounded, and the contact ring is connected to the supply, so that the two capacitors are in parallel to each other and, together with the internal resistance of the well region, form a filter for stabilizing the supply voltage. When connected to an input buffer stage of the device, the filter provides for damping the peaks produced on the supply line of the input buffer by high-current switching of the output buffers.

Integrated device with pads

The present invention is directed to a redundant UPROM cell incorporating at least one memory element of the EPROM or flash type having a control terminal and a conduction terminal to be biased, a register with inverters connected to the memory element, and MOS transistors connecting the memory element with a reference low voltage power supply. There is provided a precharge network for the conduction terminal of the flash cell and the network incorporates a complementary pair of transistors. The second transistor of the pair is a natural N-channel MOS type. With the UPROM cell is associated a circuit portion for generating a second live output signal to be applied to the control terminal of the second transistor. The circuit portion includes a timing section and a generation section for the second live output signal.

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Treviolo, Italy

Stefano Ghezzi