International Rectifier Corporation

Stefano Clemente

Brian R Pelly

Ajit Dubhashi

Cesare Bocchiola

Christopher C Chey

Rutton Ruttonsha

According to one disclosed embodiment, a power delivery circuit includes a switch for protection of a load in a reverse battery condition. The load is coupled in cascade with the protection switch, where the protection switch disconnects the load from the battery in the reverse battery condition. The protection switch does not include p-n junction diodes present in conventional protection switches using FETs. The protection switch utilizes, for example, a GaN HEMT, that does not include a p-n junction diode. Thus, the threat of internal conduction in the protection switch during a reverse battery condition is eliminated. The power delivery circuit also protects the load in a load dump condition.

Power delivery circuit having protection switch for reverse battery condition

The switching di/dt and switching dv/dt of a MOS gate controlled ('MOS-gated') power device are controlled by respectively controlling the voltage and current waveforms. Open loop control of the turn-on of the MOS-gated device is provided by coupling a common terminal of a current generator circuit, which provides a current to the gate of the MOS device, to a first resistor for controlling the switching dv/dt. At the detection of a negative dv/dt, the common terminal of the current generator circuit is then coupled to a second resistor for controlling the switching di/dt. The first and second resistors are, in turn, coupled to the source terminal fo the MOS-gated device. An analogous operation provides turn-off control of the MOS-gated power device. Closed loop control is also provided by measuring the switching dv/dt and the switching di/dt which are then fed back to the circuit to control the current supplied to the gate of the MOS-gated device. The switching di/dt can be measured by measuring the voltage difference across the length of a calibrated wire bond having a predetermined length and diameter.

Method of controlling the switching DI/DT and DV/DT of a MOS-gated power

A method and apparatus for determining the temperature of a discrete power semiconductor from an analog integrated circuit that is copackaged with the power semiconductor on a heat sink, given a knowledge of the thermal capacitances of the power semiconductor and of the analog integrated circuit, the thermal resistance between the power semiconductor and the analog integrated circuit, the thermal resistances between the power semiconductor and the heat sink and between the analog integrated circuit and the heat sink. The method includes determining the voltage across the power semiconductor and the current through the power semiconductor, thereby determining the power dissipated in the power semiconductor, determining the temperature of the analog integrated circuit, determining the heat sink temperature, using the thermal capacitances, heat sink temperature and thermal resistances to set coefficients of an asymptotic observer system, providing the voltage and current and the temperature of the analog integrated circuit to the asymptotic observer system, and providing as an output from the asymptotic observer system the temperature of the discrete power semiconductor.

Temperature detection of power semiconductors performed by a co-packaged

A current sensing circuit including a shunt resistor coupled, at one end, to the low-side transistor of a half bridge circuit and, at its other end, to a load. The voltage sensed across the shunt resistor is proportional to the current delivered to the load. A level shifting circuit is provided to transpose the sensed voltage to a low voltage signal which can be fed back to control commutation of the transistors in the half bridge circuit.

Circuit for sensing motor load current

A circuit for improving output voltage regulation of a power factor control stage providing power to a load. The circuit includes a voltage reference generating circuit that produces a voltage signal that is in phase lock with an input alternating current power line signal but is independent of voltage excursions of the alternating current line signal and unwanted voltage harmonics. The circuit also includes a control circuit receiving the voltage reference signal for controlling an electronic switch coupled to an input line providing power to the load. The electronic switch is pulsed on and off by the control circuit to force the current in the input line to the load to follow the reference voltage. The input alternating current line current is thus maintained in a substantially constant predetermined phase relationship with the input alternating current line voltage.

Method and circuit to improve output voltage regulation and noise

A power interface circuit includes a low voltage control chip and a separate, high voltage power chip contained in a common package. The high voltage power chip includes a power switching semiconductor device, such as a thyristor or power MOSFET, and is controlled under the influence of the control chip. Operating power for the low voltage control chip is provided from an auxiliary portion of the high voltage power chip. Such auxiliary portion comprises a voltage regulator, which derives its power from a high voltage lead in the power device. The high voltage lead may comprise a lead on which high voltage power is supplied for power switching purposes. The low voltage control chip may include a high degree of 'intelligence', or logic functions, for controlling the power switching device, since the low voltage device may be a microprocessor or other device that can be fabricated with a high density of control elements.

Power interface circuit with control chip powered from power chip

A switching power supply is disclosed using a single transistor circuit which provides a constant output voltage for a range of input voltages extending from a nominal 115 volt power supply to a nominal 220/240 volt power supply without requiring a change in the circuit configuration throughout the range of input voltages. The circuit is disclosed in connection with a single transistor forward converter circuit, in which the transformer winding of the converter circuit is provided with a uni-directional clamp to prevent the transformer voltage of a given polarity from exceeding the clamping voltage magnitude. By clamping one polarity of the transformer voltage which is in series with the switching transistor, the maximum peak-to-peak voltage on the transistor is reduced from that which would be produced in the absence of clamping and enables the use of a power MOSFET transistor for the circuit. The clamping circuit is disclosed as a zener clamp and as a circuit including a parallel resistor and capacitor and series diode.

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Rolling Hills Estate, CA, United States of America

Stefano Clemente