Stmicroelectronics S.r.l.

Stmicroelectronics (rousset) Sas

Stefano Catalano

Antonino Mondello

Giuseppe Guarnaccia

Antonino Giuseppe Fontana

Cyril Pascal

Nelly Feldman

In an embodiment a One-Time Programmable (OTP) memory controller includes a data register, a given number K of shadow-registers, wherein the number K is smaller than a given number N of memory slots of an OTP memory area, a communication interface configured to receive a read request requesting the data of a given memory slot and a control circuit configured to receive a preload start signal and a shadow-register preload enable signal, wherein the control circuit is configured to manage a preload phase and a data-read phase.

One-time programmable (OTP) memory controller with a control circuit configured to assert a pre-load start signal and a pre-load end signal, related processing system, integrated circuit and method

According to one aspect, a system-on-a-chip is proposed which includes a memory storage, a computation circuit, a comparison circuit, and a validation circuit. The memory storage is configured to store an external software module. The computation circuit is configured to compute several modified software modules from the external software module and compute check values by iteration until obtaining a final check value. Each check value is computed at least from a given modified software module and a check value previously computed, starting with a predefined initial check value. The comparison circuit is configured to compare the final check value to an expected value stored in the system-on-a-chip. The validation circuit is configured to validate the external software module when the final check value is equal to the expected value.

Method for validating an external software module for its use by a system-on-a-chip

A system for testing an integrated circuit including components for receiving clock signals corresponding to different clock domains includes a pin of the integrated circuit to receive a test clock signal for components included in different clock domains, clock gating cells integrated in the integrated circuit to direct said test clock signal from the pin towards components included in respective clock domains and, coupled to each of the gating cells, a dedicated flip-flop for a respective clock domain, the dedicated flip-flop being also integrated in the integrated circuit to effect on the cell to which it is coupled a clock gating function during testing of the integrated circuit.

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Catania, Italy

Stefano Catalano