International Business Machines Corporation

Stefanie Ruth Chiras

Michael Wayne Lane

Timothy Joseph Dalton

John Peter Karidis

Michele M Franceschini

Mayank Sharma

Chih-Chao Yang

Lawrence Alfred Clevenger

Luis Alfonso Lastras-Montano

Thomas Mittelholzer

Thomas M Shaw

Yun-Yu Wang

James J Demarest

Darryl D Restaino

Robert Rosenberg

Philip L Flaitz

Chester T Dziobkowski

James R Lloyd

Daniel C Edelstein

Cyril Cabral, Jr

Hariklia Deligianni

Matthew Joseph Breitwisch

Terry Allen Spooner

Emanuel Israel Cooper

Carlos Juan Sambucetti

Roger W Cheek

Ibrahim M Elfadel

Derren Neylon Dunn

Judith Marie Rubino

Andrew John Kellock

Roger Y Tsai

Sampath Purushothaman

Matthew Earl Colburn

Karthick Rajamani

Elbert Emin Huang

Sandra Guy Malhotra

Roy Rongqing Yu

Da-Yuan Shih

Jente Benedict Kuang

Satyanarayana Venkata Nitta

Gary Dale Carpenter

Freeman Leigh Rawson, Iii

Chandrasekhar Narayan

Jeffrey Curtis Hedrick

Shyng-Tsong Chen

Kaushik Arun Kumar

Christy Sensenich Tyberg

Kelly Malone

Donald W Henderson

Yu-Ting Cheng

Henry Atkinson Nye, Iii

Luis A Lastras

Alexandre Peixoto Ferreira

Stephen James Kilpatrick

Philippe Mark Vereecken

Fenton Reed Mc Feely

Sung-Kwon Kang

Darren N Dunn

Robert Rosenburg

A processor includes a processor core, a cache, and a tracker. The processor core is configured to execute persistent write instructions and receive notifications of completed persistent write instructions. The tracker is configured to track the completion state of a persistent write instruction.

Asynchronous persistent stores for transactions

Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.

Memory programming for a phase change memory cell

Techniques for writing to memory using adaptive write techniques. An adaptive write technique includes receiving at a computer a message including a plurality of symbols. The message is written to a memory. The writing to memory includes performing for each symbol in the message: writing a data value to a memory location in the memory and reading contents of the memory location after the data value has been written. The data value is determined at the computer in response to the symbol and to the contents of any memory locations previously read as part of writing the message to the memory. It is determined at the computer if the contents of the memory locations reflect the message. The writing is restarted at the computer in response to determining that the contents of the memory locations do not reflect the message.

Writing to memory using adaptive write techniques

A method for writing in a memory system that includes receiving an address corresponding to a memory location in a memory, receiving a desired content to be written, encoding the desired content into a symbol, and writing the symbol to the memory location using an iterative write process of at least one write and one read to the memory location. The iterative write process includes determining if the symbol was successfully written to the memory location and exiting the iterative write process in response to the symbol being successfully written to the memory location. The iterative write process also includes determining if a halt condition has been met and exiting the iterative write process if the halt condition has been met. Once the iterative write process has been exited, the memory location may be identified as a candidate for being written with a special symbol.

Writing a special symbol to a memory to indicate the absence of a data signal

Iteratively writing contents to memory locations using a statistical model

In integrated circuit technology; an electromigration and diffusion sensitive conductor of a metal such as copper and processing procedure therefore is provided, wherein, at a planarized chemical mechanical processed interfacing surface, the conductor metal is positioned in a region of a selectable low K eff dielectric material surrounded by a material selected to be protection from outdiffusion and a source of a film thickness cap that is to form over the conductor metal and/or serve as a catalytic layer for electroless selective deposition of a CoWP capping .

Formation of aligned capped metal lines and interconnections in multilevel semiconductor structures

An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiO&#x2014; or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

Structure to improve adhesion between top CVD low-K dielectric and dielectric capping layer

A conducting material comprising: a conducting core region comprising copper and from 0.001 atomic percent to 0.6 atomic percent of one or more metals selected from iridium, osmium and rhenium; and an interfacial region. The interfacial region comprises at least 80 atomic percent or greater of the one or more metals. The invention is also directed to a method of making a conducting material comprising: providing an underlayer; contacting the underlayer with a seed layer, the seed layer comprising copper and one or more metals selected from iridium, osmium and rhenium; depositing a conducting layer comprising copper on the seed layer, and annealing the conducting layer at a temperature sufficient to cause grain growth in the conducting layer, yet minimize the migration of the one or more alloy metals from the seed layer to the conducting layer. The method further comprises polishing the conducting layer to provide a polished copper surface material, and annealing the polished copper surface material at a temperature to cause migration of the one or more metals from the seed layer to the polished surface to provide an interfacial region in contact with a copper conductor core region. The interfacial region and the copper conductor core region comprise the one or more metals.

Metal capped copper interconnect

An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiO- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer

A ball-limiting metallurgy includes a substrate, a barrier layer formed over the substrate, an adhesion layer formed over the barrier layer, a first solderable layer formed over the adhesion layer, a diffusion barrier layer formed over the adhesion layer, and a second solderable layer formed over the diffusion barrier layer.

Ball limiting metallurgy, interconnection structure including the same, and method of forming an interconnection structure

A composite material comprising a layer containing copper, and an electrodeposited CoWP film on the copper layer. The CoWP film contains from 11 atom percent to 25 atom percent phosphorus and has a thickness from 5 nm to 200 nm. The invention is also directed to a method of making an interconnect structure comprising: providing a trench or via within a dielectric material, and a conducting metal containing copper within the trench or the via; and forming a CoWP film by electrodeposition on the copper layer. The CoWP film contains from 10 atom percent to 25 atom percent phosphorus and has a thickness from 5 nm to 200 nm. The invention is also directed to a interconnect structure comprising a dielectric layer in contact with a metal layer; an electrodeposited CoWP film on the metal layer, and a copper layer on the CoWP film.

Electroplated CoWP composite structures as copper barrier layers

Copper conductor

In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.

Line level air gaps

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Peekskill, NY, United States of America

Stefanie Ruth Chiras