Freescale Semiconductor,inc.

International Business Machines Corporation

Globalfoundries Inc.

Stefan Zollner

Paul Grudowski

Veeraraghavan Dhandapani

Edward P Maciejewski

Dustin Kenneth Slisher

Christian Lavoie

Bin Yang

Bich-Yen Nguyen

Qingqing Liang

Zhen Zhang

Yu Zhu

Ahmet Serkan Ozcan

Stephen Mark Rossnagel

Voon-Yew Thean

Byoung W Min

Gregory S Spencer

Andrew John Kellock

Darren V Goedeke

An improved eFuse and method of fabrication is disclosed. A cavity is formed in a substrate, which results in a polysilicon line having an increased depth in the area of the fuse, while having a reduced depth in areas outside of the fuse. The increased depth reduces the chance of the polysilicon line entering the fully silicided state. The cavity may be formed with a wet or dry etch.

eFUSE and method of fabrication

eFuse and method of fabrication

A method for forming a silicide contact includes depositing a metal layer on silicon such that the metal layer intermixes with the silicon to form an intermixed region on the silicon; removing an unintermixed portion of the metal layer from the intermixed region; and annealing the intermixed region to form a silicide contact on the silicon. A semiconductor device comprising a silicide contact located over a silicon layer of the semiconductor device, the silicide contact comprising nickel (Ni) and silicon (Si) and having Ni amount equivalent to a thickness of about 21 angstroms or less.

Silicide contact formation

A method for forming a body contacted SOI transistor includes forming a semiconductor layer () having a body contact region (), a body access region (), and an active region (). An SOI transistor is formed in the active region by etching a metal gate structure () to have a first portion () formed over the active region, and a second portion () formed over at least part of the body access region. By implanting ions () at a non-perpendicular angle into an implant region () in the body access region so as to encroach toward the active region and/or under the second portion of the etched metal gate structure, silicide () may be subsequently formed over the body contact region and the implant region, thereby reducing formation of a depletion region () in the body access region.

Efficient body contact field effect transistor with reduced body resistance

A method for forming a semiconductor device includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode over the gate dielectric; forming an insulating layer over a sidewall of the gate electrode; defining source and drain regions in the semiconductor substrate adjacent to the insulating layer; implanting a dopant in the source and drain regions of the semiconductor substrate to form doped source and drain regions; forming a sidewall spacer adjacent to the insulating layer; forming a recess in the semiconductor substrate in the source and drain regions, wherein the recess extends directly underneath the spacer a predetermined distance from a channel regions; and forming a stressor material in the recess. The method allows the stressor material to be formed closer to a channel region, thus improving carrier mobility in the channel while not degrading short channel effects.

Method of making a semiconductor device with embedded stressor

In a semiconductor fabrication process, an epitaxial layer is formed overlying a substrate, wherein there is a lattice mismatch between the epitaxial layer and the substrate. A hard mask having an opening is formed overlying the epitaxial layer. A recess is formed through the epitaxial layer and into the substrate. The recess is substantially aligned to the opening in the hard mask. A channel region of a semiconductor device is formed in the recess.

Fabrication of a semiconductor device with stressor

A process can include forming a doped semiconductor layer over a substrate. The process can also include performing an action that reduces a dopant content along an exposed surface of a workpiece that includes the substrate and the doped semiconductor layer. The action is performed after forming the doped semiconductor layer and before the doped semiconductor layer is exposed to a room ambient. In particular embodiments, the doped semiconductor layer includes a semiconductor material that includes a combination of at least two elements selected from the group consisting of C, Si, and Ge, and the doped semiconductor layer also includes a dopant, such as phosphorus, arsenic, boron, or the like. The action can include forming an encapsulating layer, exposing the doped semiconductor layer to radiation, annealing the doped semiconductor layer, or any combination thereof.

Process of forming an electronic device including a doped semiconductor layer

An anneal of an epitaxially grown crystalline semiconductor layer comprising a combination of group-IV elements. The layer contains at least one of the group of carbon and tin. The layer of epitaxially grown material is annealed at a temperature substantially in a range of 1,000 to 1,400 degrees Celsius for a period not to exceed 100 milliseconds within 10% of the peak temperature. The anneal is performed for example with a laser anneal or a flash lamp anneal. The limited-time anneal may improve carrier mobility of a transistor.

Anneal of epitaxial layer in a semiconductor device

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Hopewell Junction, NY, United States of America

Stefan Zollner