Siltronic Ag

Stefan Welsch

Axel Beyer

Christof Weber

Semiconductor wafers having a subsurface-referenced nanotopography of the upper side surface of less than 6 nm, expressed as a maximum peak-to-valley distance on a subsurface and referenced to subsurfaces with an area content of 25 mm×25 mm, are produced from a workpiece by feeding the workpiece through a wire web tensioned between wire guide rollers and divided into wire groups, the wires producing kerfs as the wires engage the workpiece. For each of the wire groups, a placement error of the kerfs of the wire groups is used to compensate movements of the wires of the wire group as a function of the placement error, in a direction perpendicular to the running direction of the wires during feeding of the workpiece through the arrangement of wires, by activating at least one drive element.

Method for producing semiconductor wafers using a wire saw, wire saw, and semiconductor wafers made of monocrystalline silicon

The invention relates to an epitaxially coated semiconductor wafer, processed by a method in which the semiconductor wafer is disposed on a susceptor in a coating apparatus and processed, wherein an etching gas is passed through the coating apparatus in an etching step. A first side of the semiconductor wafer which has been subjected to a polishing operation by CMP, or a second side of the semiconductor wafer opposite the first side, is coated with a protective layer before processing. The resulting wafer has exceptional geometry, as reflected by low ESFQR values.

Method, control system, and system for machining a semiconductor wafer, and semiconductor wafer

Semiconductor wafers are produced from a workpiece by means of a wire saw, by feeding the workpiece through an arrangement of wires tensioned between wire guide rollers and divided into wire groups, the wires moving in a running direction producing kerfs as wires engage the workpiece. For each of the wire groups, a placement error of the kerfs of the wire groups determined, and for each of the wire groups compensating movements of the wires of the wire group are induced as a function of the placement error, in a direction perpendicular to the running direction of the wires during feeding of the workpiece through the arrangement of wires, by activating at least one drive element.

The invention relates to a method of processing a semiconductor in the semiconductor wafer is disposed on a susceptor in a coating apparatus and processed, wherein an etching gas is passed through the coating apparatus in an etching step. The invention further relates to a control system for controlling a coating apparatus for processing a semiconductor water, to a plant for processing a semiconductor wafer having a coating apparatus which comprises the control system, and a semiconductor wafer. A first side of the semiconductor wafer which has been subjected to a polishing operation by CMP, or a second side of the semiconductor wafer opposite the first side, is coated with a protective layer before processing.

Semiconductor wafers, are processed using minimally three processing operations: a first double-sided polishing operation, a second chemical-mechanical polishing operation and an epitaxial coating operation. A control system for conducting the method defines at least one operating parameter for the processing operations specifically based on at least one wafer parameter measured on the semiconductor wafer after processing in at least one processing operation, based on an actual state of a processing apparatus with which the respective processing operation is conducted, and based on optimizing wafer parameters for flatness after the wafer has undergone all three processing operations instead of optimizing each individual processing step for optimal flatness.

Growing community of inventors

Polling, Germany

Stefan Welsch