Infineon Technologies Ag

Other

International Business Machines Corporation

Infineon Technologies North America Corp.

Stefan Weber

Roy Charles Iggulden

Lawrence Alfred Clevenger

Kenneth Parker Rodbell

Florian Schnabel

Ronald G Filippi

Mark Hoinkis

Rainer Florian Schnabel

Jeffrey P Gambino

Chao-Kun Hu

Lynne Marie Gignac

Axel Brintzinger

Horatio Seymour Wildman

Sven Schmidbauer

Maria Ronay

Herbert Palm

Larry Clevenger

Chenting Lin

Alexander Ruf

Hans W Poetzlberger

Dirk T&ouml;bben

Jeffery L Hurd

Ebrahim A Mehter

A conductor for interconnecting integrated circuit components having improved reliability. The conductor includes a liner surrounding at least three surfaces of the conductor, producing a low textured conductor. It has been found that low textured conductor results in improved electromigration lifetime.

Device interconnection

High aspect ratio vias formed in a first insulating layer covering a semiconductor substrate (body) are filled with conductors in a manner that both reduces the number of processing steps and allows an alignment tool (stepper) to align to alignment and overlay marks. Sidewalls and a bottom of each via are coated with a composite layer of titanium, titanium nitride, and a chemical vapor deposited seed layer of aluminum. A physical vapor deposited layer of aluminum is then formed while the structure is heated to about 400 degrees C. to completly fill the vias and to overfill same to form a blanket layer of aluminum above the first insulating layer ( ). The blanket layer of aluminum is then patterned and portions not covered by the pattern are removed to result in columns of aluminum. A second insulating layer is then formed around the columns of aluminum. The ends of the columns at a top of the second insulating layer lie in a relatively common plane to which steppers can relatively easily align patterns.

Semiconductor structure and method of fabrication including forming aluminum columns

An antifuse (e.g., ) is formed in an integrated circuit through the use of a block mask (e.g., photoresist ) during in situ antifuse dielectric formation. Generally, the mask allows self-aligned oxidation of an oxidizable metal (e.g., aluminum ) to form the antifuse dielectric (e.g., aluminum oxide ), while preventing oxidation of non-programmable or fixed connections (e.g., conductive stack ). The number of mask, deposition, or etching steps may be reduced relative to prior art methods. In addition, a fixed connection may be formed during the formation of and at the same level as the antifuse link.

Method of forming a self-aligned antifuse link

A dual damascene process capable of reliably producing aluminum interconnects that exhibit improved electromigration characteristics over aluminum interconnects produced by conventional RIE techniques. In particular, the dual damascene process relies on a PVD-Ti/CVD-TiN barrier layer to produce aluminum lines that exhibit significantly reduced saturation resistance levels and/or suppressed electromigration, particularly in lines longer than 100 micrometers. The electromigration lifetime of the dual damascene aluminum line is strongly dependent on the materials and material fill process conditions. Significantly, deviations in materials and processing can result in electromigration lifetimes inferior to that achieved with aluminum RIE interconnects. In one example, current densities as high as 2.5 MA/cm are necessary to induce a statistically relevant number of fails due to electromigration.

Aluminum-based metallization exhibiting reduced electromigration and method therefor

A method of enriching the surface of a substrate with a solute material that was originally dissolved in the substrate material, to yield a uniform dispersion of the solute material at the substrate surface. The method generally entails the use of a solvent material that is more reactive than the solute material to a chosen reactive agent. The surface of the substrate is reacted with the reactive agent to preferentially form a reaction compound of the solvent material at the surface of the substrate. As the compound layer develops, the solute material segregates or diffuses out of the compound layer and into the underlying substrate, such that the region of the substrate nearest the compound layer becomes enriched with the solute material. At least a portion of the compound layer is then removed without removing the underlying enriched region of the substrate. For microcircuit applications, the method can be used to enrich the surface of an aluminum line with elemental copper to improve the electromigration resistance of the line.

Method of forming a solute-enriched layer in a substrate surface and article formed thereby

High aspect ratio vias formed in a first insulating layer covering a semiconductor substrate (body) are filled with conductors in a manner that both reduces the number of processing steps and allows an alignment tool (stepper) to align to alignment and overlay marks. Sidewalls and a bottom of each via are coated with a composite layer of titanium, titanium nitride, and a chemical vapor deposited seed layer of aluminum. A first physical vapor deposited layer of aluminum is then formed while the semiconductor body is heated to about 400 degrees C. to completely the vias and to overflow same to form a blanket layer of aluminum above the first insulating layer. A second physical vapor deposited layer of aluminum is then formed over the first blanket layer of aluminum while the structure is heated to about 200 degrees C. to form a second blanket layer of aluminum over the first. The second blanket layer of aluminum is then patterned and portions not covered by the pattern are removed, as well as portions of the first blanket layer below the removed portions of the second blanket layer to result in columns of aluminum. A second insulating layer is then formed around the columns of aluminum. The ends of the columns of aluminum at a top of the second insulating layer lie in a common plane to which steppers can relatively easily align patterns.

Semiconductor structure and method of fabrication

A method is provided in which intermediate sized structures can be filled without forming voids during the fill process. The methods involve use of a sequence of CVD/PVD/CVD/PVD steps. The methods are especially effective for filling &ldquo;intermediate&rdquo; size features in damascene and dual damascene structures.

CVD/PVD/CVD/PVD fill process

A microelectronic structure is formed on a first layer or a substrate. The first layer or substrate is formed with grooves and contact openings. A metal nitride layer of TiN or WN covers the first layer or the substrate at least partially. An alpha-phase tantalum layer is deposited on top of the metal nitride layer. Finally, a metal is deposited to completely fill the grooves and the contact openings.

Method of making a microelectronic structure

Growing community of inventors

Dresden, Germany

Stefan Weber