Infineon Technologies Dresden Gmbh

Infineon Technologies Ag

Qimonda Ag

Infineon Technologies Austria Ag

Infineon Technologies Dresden Gmbh & Co . Kg

Markus Hörmann Vermietungen Und Verpachtungen

Stefan Tegen

Marko Lemke

Rolf Weis

Klaus Muemmler

Peter Baars

Dirk Manger

Matthias Kroenke

Thomas Happ

Alessandro Ferrara

Joachim Weyers

Armin Tilke

Ulrike Gruening-von Schwerin

Adrian Finney

Uwe Rudolph

Martin Bartels

Marc Probst

Franz Stueckler

Richard Hensch

Frank Hoffmann

Andreas Pribil

Joern Regul

Franz Hirler

Anton Mauder

Oliver Blank

Lothar Risch

Uwe Wahl

Mirko Vogt

Markus Schmitt

Andreas Walter

Markus Münch

Stefan Slesazeck

Odo Wunnicke

Thomas Bertrams

Johannes Von Kluge

Patrick Schindler

Alexander Sieck

Daniel Koehler

Andreas Boehm

Andrei Josiek

Uta Mierau

Andreas Eifler

Christoph Kubasch

Igor Kasko

A transistor device includes a semiconductor substrate having a first major surface, a cell field, and an edge termination region laterally surrounding the cell field. The cell field includes elongate trenches that extend from the first major surface into the semiconductor substrate and that are positioned substantially parallel to one another such that one or more inner elongate trenches are arranged between two outermost elongate trenches and elongate mesas, each elongate mesa being formed between neighbouring elongate trenches. The elongate mesas include a drift region, a body region on the drift region and a source region on the body region. In a top view, one or both of the outermost elongate trenches has a different contour from the one or more inner elongate trenches.

Transistor device

The application relates to a semiconductor die including a device in an active area of the die. The device includes a field electrode region formed in a field electrode trench extending vertically into a semiconductor body. The field electrode region includes a first and a second field electrode stacked vertically above each other in the field electrode trench. An edge termination structure laterally between the active area and a lateral edge region of the die includes a first and a second shield electrode arranged laterally consecutive between the active area and the lateral edge region to stepwise decrease an electrical potential between the edge region and the active area.

Semiconductor die including an edge termination structure laterally between an active area and a lateral edge region of the die

The disclosure relates to a semiconductor die with a transistor device, which has a channel region formed in a semiconductor body, a gate region aside the channel region, for controlling a channel formation, a drift region formed in the semiconductor body, and a field electrode in a field electrode trench, which extends from a frontside of the semiconductor body vertically into the drift region, wherein an insulating layer is formed on the frontside of the semiconductor body and a frontside metallization is formed on the insulating layer, and wherein a capacitor electrode is formed in the insulating layer, which is conductively connected to at least a portion of the field electrode.

Semiconductor die with a power device and method of manufacturing the same

A transistor device includes a semiconductor substrate having a first major surface, a cell field and an edge termination region laterally surrounding the cell field. The cell field includes: elongate active trenches that extend from the first major surface into the semiconductor substrate, a field plate and a gate electrode being positioned in each elongate active trench, the gate electrode being arranged above and electrically insulated from the field plate; and elongate mesas, each elongate mesa being formed between neighbouring elongate active trenches, the elongate mesas comprising a drift region, a body region on the drift region and a source region on the body region.

Transistor device having a field plate

Transistor device having a field plate in an elongate active trench

In an embodiment, a method of forming a field plate in an elongate active trench of a transistor device is provided. The elongate active trench includes a first insulating material lining the elongate active trench and surrounding a gap and first conductive material filling the gap. The method includes selectively removing a first portion of the first insulating material using a first etch process, selectively removing a portion of the first conductive material using a second etch process, and forming a field plate in a lower portion of the elongate active trench and selectively removing a second portion of the first insulating material using a third etch process. The first etch process is carried out before the second etch process and the second etch process is carried out before the third etch process.

Transistor device and method of forming a field plate in an elongate active trench of a transistor device

An electronic circuit is disclosed. The electronic circuit includes: a first transistor device integrated in an inner region of a first semiconductor body; a level shifter integrated in a level shifter region of the first semiconductor body, the level shifter region located in an edge region surrounding the inner region of the semiconductor body; and a drive circuit integrated in a drive circuit region in the edge region of the first semiconductor body, the drive circuit configured to receive a first input signal from a first input and drive the first transistor device based on the first input signal, the drive circuit region arranged closer to the inner region than the level shifter region.

Electronic circuit with a transistor device, a level shifter and a drive circuit

An electronic circuit is disclosed. The electronic circuit includes: a first transistor device integrated in an inner region of a first semiconductor body; and a first drive circuit integrated in a first drive circuit region of the semiconductor body. The first drive circuit is configured to be connected to a level shifter and to drive a second transistor device. The first drive circuit region is located in an edge region surrounding the inner region of the semiconductor body.

Electronic circuit with a transistor device and a level shifter

A method includes partly removing a supporting layer arranged between a first semiconductor layer and a second semiconductor layer using an etching process to form at least one undercut between the first semiconductor layer and the second semiconductor layer, at least partly filling the at least one undercut with a first material having a higher thermal conductivity than the supporting layer, and forming a sensor device in or on the second semiconductor layer. Semiconductor arrangements and devices produced by the method are also described.

Method for producing a semiconductor arrangement

A method of manufacturing a semiconductor device includes forming an amorphous silicon layer over a first isolation layer. The method further includes simultaneously forming a gate oxide layer of a transistor device and transforming the amorphous silicon layer into a polycrystalline silicon layer by a thermal oxidation process. Herein a cover oxide layer is formed on the polycrystalline silicon layer.

Method of manufacturing a semiconductor device

Embodiments provide a method for manufacturing a bipolar junction transistor, comprising:

Method for manufacturing a bipolar junction transistor

A method for forming a semiconductor device includes forming a body implant region of a vertical field effect transistor arrangement in a semiconductor substrate and forming a plurality of compensation regions in the semiconductor substrate after forming the body implant region of the vertical field effect transistor arrangement. Further embodiments of methods for forming a semiconductor device are described.

Method for forming vertical field effect transistor devices having alternating drift regions and compensation regions

According to various embodiments, an integrated circuit structure may include: an electronic circuit being arranged on a surface of a carrier; and a solid state electrolyte battery being at least partially arranged within the carrier, wherein at least a part of the solid state electrolyte battery being arranged within the carrier is overlapping with the electronic circuit along a direction parallel to the surface of the carrier.

Integrated circuit structure and a battery structure

A semiconductor device includes a semiconductor substrate having a first side, and a trench structure having a bottom and a sidewall. The bottom has at least first and second bottom portions laterally adjacent to one another. Each bottom portion has a concave shape with a ridge formed between the first and second bottom portions. An insulating material covers the sidewall and first bottom portion of the trench structure while leaving the second bottom portion uncovered. A mesa region extends to the first side of the substrate and forms the sidewall of the trench structure. The device also includes a first silicide layer on a top region of the mesa region, a second silicide layer on the second bottom portion of the trench structure, a first metal layer on and in contact with the first silicide layer, and a second metal layer on and in contact with the second silicide layer.

Semiconductor device having silicide layers

A method for manufacturing a plurality of nanowires, the method including: providing a carrier comprising an exposed surface of a material to be processed and applying a plasma treatment on the exposed surface of the material to be processed to thereby form a plurality of nanowires from the material to be processed during the plasma treatment.

Apparatus comprising a plurality of nanowires

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Dresden, Germany

Stefan Tegen