Qimonda Ag

Infineon Technologies Ag

Stefan Slesazeck

Alexander Sieck

Till Schloesser

Stefan Tegen

Dirk Manger

Klaus Muemmler

Ulrike Gruening-von Schwerin

Bernd Goebel

Tobias Mono

Arnd Scholz

Lars Dreeskornfeld

An integrated circuit is provided comprising an array of memory cells connected by word and bit lines, respectively, wherein each memory cell comprises a thyristor structure, an anode terminal that connects the thyristor structure with a respective bit line, a gate terminal that connects the thyristor structure with a respective word line, and a cathode terminal. The integrated circuit further comprises a drive/sensing circuitry configured to apply a first sequence of voltage signals at the anode terminal and the gate terminal, wherein the voltage signals are defined with respect to the cathode terminal. The first sequence comprises a first voltage signal at the anode terminal, a second voltage signal at the gate terminal, and thereafter a combination of a third voltage signal at the anode terminal and a fourth voltage signal at the gate terminal, wherein the third voltage signal is lower than the first voltage signal and lower than the fourth voltage signal.

Integrated circuit comprising a thyristor and method of controlling a memory cell comprising a thyristor

According to one embodiment of the present invention, an integrated circuit is provided including a plurality of resistivity changing memory elements and a plurality of memory element select devices, wherein the select devices are floating body select devices.

Integrated circuit and method of operating an integrated circuit

A memory cell array includes a plurality of floating body memory cells, which are arranged in cell rows, and world lines, wherein each word line is configured to control memory cells associated with a pair of cell rows. The memory cell array also includes bitlines, wherein each bitline is electrically connected to an individual memory cell of each pair of the cell rows.

Memory cell array comprising floating body memory cells

A semiconductor memory device includes circuitry coupled to a plurality of memory cells with transistors. The circuitry is configured to change a potential of a body of the transistor to a degree depending on a charging state of the body. A gate electrode of the transistor is maintained in a non-addressed state.

Semiconductor device, an electronic device and a method for operating the same

An integrated circuit including a memory device comprises an array portion comprising memory cells and conductive lines, an upper surface of the conductive lines being disposed beneath a surface of a semiconductor substrate, and a support portion comprising transistors of a first type, the transistors of the first type comprising a first gate electrode including vertical portions that are vertically adjacent to a channel of the transistor of the first type.

Integrated circuit and method of manufacturing an integrated circuit

A memory cell array includes a plurality of active areas in which a plurality of memory cells are formed. A memory cell includes a storage capacitor, a transistor at least partially formed in a semiconductor substrate with a substrate surface, the transistor including a first source/drain region. A second source/drain region being formed adjacent to the substrate surface, a channel region connecting the first and second source/drain regions. The first source/drain region is formed adjacent to the substrate surface. The channel region is disposed in the semiconductor substrate, and a gate electrode. Rows of the active areas are separated from each other by isolation grooves that extend along a first direction. A first and a second word lines are disposed on either lateral sides of each of the rows of active areas. The first and the second word lines are connected with each other via the gate electrodes of the transistors of the corresponding row of active areas.

Memory cell array and method of manufacturing the same

The present invention relates to a manufacturing method for a recessed channel array transistor and a corresponding recessed channel array transistor. In one embodiment, the present invention uses a self-adjusting spacer on the substrate surface to provide the required distance between the gate and the source/drain regions. Thus, the requirements regarding the tolerances of the lithography in the gate contact plane are diminished.

Manufacturing method for a recessed channel array transistor and corresponding recessed channel array transistor

A vertical memory cell comprises a storage capacitor, the inner electrode of which is formed in a deep trench, and a vertical selector transistor. The selection transistor has an upper source/drain region and a lower source/drain region, which has emerged by outdiffusion of a dopant from the inner electrode. A gate electrode, which in each case controls a current flow between two assigned source/drain regions, is formed, in segments, as a segment of an addressing line arranged row-wise in active trenches. The provision of an auxiliary structure in the active trenches enables the addressing lines to be vertically positioned in the active trenches independently of a depth of the active trenches. Leakage currents which occur in overlap regions of the addressing lines with the inner electrode or the lower source/drain region are reduced.

Growing community of inventors

Dresden, Germany

Stefan Slesazeck