Nxp Usa, Inc.

Freescale Semiconductor,inc.

Bayerische Motoren Werke Aktiengesellschaft

Stefan Singer

Michael Rohleder

Jochen Gerster

Manfred P Thanner

Stephan Matthias Herrmann

Albrecht Neff

Osvaldo Israel Romero Cortez

Guillaume Perret

Viktor Fellinger

Josef Fuchs

Heinz Wrobel

Manfred Thanner

Disclosed are various embodiments for implementing automatic firmware rollbacks after a configured number of attempts to execute the latest firmware update associated with an electronic computing unit have occurred. In a computing device, such as an electronic computing unit, a watchdog automatically generates a system reset in response to a software fault. A reset counter is configured to count a number of system resets generated by the watchdog. In response to the occurrence of the watchdog, a configurable threshold value associated with a threshold data record is compared with the value associated with the reset counter. In response to a determination that the threshold value associated with the threshold data record is greater than or equal to the value associated with the reset counter, a rollback application is executed such that the rollback application performs a swap of a first version of a firmware with a second version of the firmware.

Automatic firmware rollback

A method of performing compression of image data for at least one image is described. The method comprises receiving image data of at least a part of the at least one image, encoding the received image data into at least one compressed data block, applying at least one bandwidth limit to the at least one compressed data block, and outputting the at least one bandwidth limited compressed data block to a buffer. The method further comprises dynamically updating the at least one bandwidth limit applied to the at least one compressed data block base at least partly on a fill level of the buffer.

Method and apparatus for performing compression of image data

A task control circuit maintains, in response to task event information, a task information queue that includes task information for a plurality of tasks. Based upon the task information in the task information queue, a future task switch condition is identified as corresponding to a task switch time for a particular task of the plurality of tasks. A load start time is determined for a set of instructions for the particular task. A pre-fetch request is generated to load the set of instructions for the particular task into the memory circuit. The pre-fetch request is forwarded to a hardware loader circuit. In response to the task switch time, a task event trigger is generated for the particular task. The hardware loader circuit is used to load, in response to the pre-fetch request, the set of instructions from a non-volatile memory into the memory circuit.

Hardware controlled instruction pre-fetching

Pre-fetching instructions for tasks of an operating system (OS) is provided by calling a task scheduler that determines a load start time for a set of instructions for a particular task corresponding to a task switch condition. The OS calls, and in response to the load start time, a loader entity module that generates a pre-fetch request that loads the set of instructions for the particular task from a non-volatile memory circuit into a random access memory circuit. The OS calls the task scheduler to switch to the particular task.

Instruction pre-fetching

An embedded computer system includes a processor, an interrupt source, an interrupt controller and a cache memory subsystem. In response to a request from the processor to read a data element, the cache memory subsystem fills cache lines in a cache memory with data elements read from an upper-level memory. While filling a cache line the cache memory subsystem is unable to respond to a second request from the processor which also requires a cache line fill. In response to receiving an indication from an interrupt source, the interrupt controller provides an indication substantially simultaneously to the processor and to the cache memory subsystem. In response to receiving the indication from the interrupt controller, the cache memory subsystem terminates a cache line fill and prepares to receive another request from the processor.

System and method for cache memory line fill using interrupt indication

A unit () used to control a segment liquid crystal display (). The segment liquid crystal display () includes at least a backplane electrode () and at least a front plane electrode () both associated with a same segment of the segment liquid crystal display (). The unit () includes a controller () in order to generate a pulse-width-modulated control signal () that has two voltage levels and a variable duty cycle. The unit () further includes an integrator () to integrate the pulse-width-modulated control signal () and to provide an integrated control signal () which has more than two discrete voltage levels corresponding to different variable duty cycle values. An output of the unit () supplies the integrated control signal () to the at least a backplane electrode () or to the at least a front plane electrode () so that visibility of the same segment in the segment liquid crystal display () can be controlled. By having a pulse-width-modulated control signal () with only two voltage levels and different duty cycle values generated by the controller (), and by having the integrator () integrating said pulse-width-modulated control signal (), more than two different discrete voltage levels are generated to control the at least a backplane electrode () or at least a front plane electrode () without the need to use an application specific segment liquid crystal interface in the unit (), thereby abating the cost of implementation of the unit ().

Control unit for a segment liquid crystal display and a method thereof

A system on chip having two or more responder units and two or more protection units is provided. Each of the responder units comprises a set of responder elements. Each of the protection units is associated with and protects one of the responder units and is arranged to provide a group mapping. The group mapping assigns one or more group identifiers to each of the responder elements of the respective responder unit.

System on chip

A method of data streaming in a streaming system () that comprises a processor () and a controller () operably coupled to a streaming peripheral () via a shared interconnect () is described. The method comprises at the controller, receiving at least one descriptor that points to at least one header data element in memory and at least one payload buffer element in the streaming peripheral (); reading the at least one descriptor () by the controller (); fetching by the controller the at least one header data element from memory and the at least one payload element from the payload buffer () in the streaming peripheral () referred to by the descriptor ().

Method and apparatus for network streaming

In a system on chip responder units comprise one or more responder elements and is associated with one or more protection units. A request analysis unit is arranged to receive from a requesting requestor unit a request for access to one or more target responder elements among responder elements within a target responder unit among the responder units. The request analysis unit determines relevant protection data based on the request and an authorization list, which comprises one or more entries For each entry of the authorization list: taking access requirements specified by the respective entry into account if one or more of the target responder elements are part of the group of responder elements specified by the respective entry. The request analysis unit provides the relevant protection data to one or more target protection unit(s) associated with the responder unit(s), and located in a hierarchical path between the requesting requestor unit requestor unit and the target responder unit. The target protection unit(s) are arranged to perform a protective action for the target responder elements based on relevant protection data.

A system comprises one or more slave elements operably coupled to a plurality of master devices. A central protection function is operably coupled to a first communication bus and configured to control data flow between the one or more slave elements and the plurality of master devices via the communication bus.

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Vaterstetten, Germany

Stefan Singer