International Business Machines Corporation

Lam Research Corporation

Globalfoundries Inc.

Siemens Aktiengesellschaft

Stefan Schmitz

Sanjay C Mehta

Kangguo Cheng

Junli Wang

Shom Ponoth

Bruce Bennett Doris

Chun-chen Yeh

Hemanth Jagannathan

Balasubramanian S Haran

Theodorus E Standaert

John Christopher Arnold

Nicolas J Loubet

Pranita Kulkarni

Christopher N Collins

James Patrick Norum

Michael Goss

Phil Friddle

Ali Khakifirooz

Tenko Yamashita

Effendi Leobandung

Veeraraghavan S Basker

David V Horak

Steven J Holmes

Sivananda K Kanakasabapathy

Amlan Majumdar

Ravikumar Ramachandran

Huiming Bu

Yunpeng Yin

Raghavasimhan Sreenivasan

Randolph F Knarr

Rangarajan Jagannathan

Xuefeng Hua

Bala S Haran

Bhaskar Nagabhirava

Harris C Jones

Prabhakara Gopaladasu

Peng Wang

Adarsh Basavalingappa

Thomas N Adam

Pranita Kerber

K Paul Muller

Rajiv M Ranade

Jin J Wu

Len Yuan Tsou

William A Cavaliere

Jeffrey J Brown

George A Kaplita

Noel Sun

Naveed Ansari

Wilson Tong Lee

Jae Ho Lee

Changwoo Lee

A method for selectively etching an etch layer with respect to a mask is provided. An etch process is provided comprising a plurality of etch cycles, wherein each etch cycle comprises providing a deposition phase and an etch phase. The deposition phase comprises providing a flow of a deposition phase gas, comprising a fluorocarbon or hydrofluorocarbon containing gas and an oxygen containing gas with a fluorocarbon or hydrofluorocarbon to oxygen ratio, providing a RF power, which forms the deposition phase gas into a plasma, and stopping the deposition phase. The etch phase, comprises providing a flow of an etch phase gas, comprising a fluorocarbon or hydrofluorocarbon containing gas and an oxygen containing gas with a fluorocarbon or hydrofluorocarbon to oxygen ratio that is lower than the fluorocarbon or hydrofluorocarbon to oxygen ratio of the deposition phase gas, providing a RF power, and stopping the etch phase.

Method for selectively etching with reduced aspect ratio dependence

A method of performing a sidewall image transfer (SIT) process includes arranging a substrate within a substrate processing chamber, wherein the substrate includes a mandrel layer formed on the substrate and etching the mandrel layer to form a plurality of mandrels. The method further includes, without removing the substrate from within the substrate processing chamber and subsequent to etching the mandrel layer, depositing a thin spacer layer such that the thin spacer layer is formed on upper surfaces of the plurality of mandrels, sidewalls of the plurality of mandrels, and portions of the substrate between the sidewalls of the plurality of mandrels, subsequent to depositing the thin spacer layer, etching the thin spacer layer to remove the thin spacer layer from the upper surfaces of the mandrels and the portions of the substrate between the sidewalls of the plurality of mandrels such that only the thin spacer layer formed on the sidewalls of the plurality of mandrels remains, and, subsequent to etching the thin spacer layer from the upper surfaces of the mandrels and the portions of the substrate between the sidewalls of the plurality of mandrels, etching the plurality of mandrels to remove the plurality of mandrels from the substrate such that only the thin spacer layer formed on the sidewalls of the plurality of mandrels remains on the substrate.

Systems and methods for performing in-situ deposition of sidewall image transfer spacers

A field effect transistor device includes a fin including a semiconductor material arranged on an insulator layer, the fin including a channel region, a hardmask layer arranged partially over the channel region of the fin, a gate stack arranged over the hardmask layer and over the channel region of the fin, a metallic alloy layer arranged on a first portion of the hardmask layer, the metallic alloy layer arranged adjacent to the gate stack, and a first spacer arranged adjacent to the gate stack and over the metallic alloy layer.

Replacement metal gate finFET

A semiconductor structure which includes: a fin on a semiconductor substrate; and a gate structure wrapped around the fin. The gate structure includes: spaced apart spacers to form an opening, the spacers being perpendicular to the fin, the spacers having a height with respect to the fin; a high-k dielectric material in the opening and over the fin, the high-k dielectric material in contact with the spacers and a bottom of the opening; a work function metal in contact with the high-k dielectric material that is over the fin, the spacers and the bottom of the opening, the work function metal that is in contact with the high-k dielectric material having a height in the opening that is less than the height of the spacers, the high-k dielectric material and the work function metal only partially filling the opening; and a metal completely filling the opening.

Replacement metal gate

A method for fabricating a field effect transistor device includes depositing a hardmask over a semiconductor layer depositing a metallic alloy layer over the hardmask, defining a semiconductor fin, depositing a dummy gate stack material layer conformally on exposed portions of the fin, patterning a dummy gate stack by removing portions of the dummy gate stack material using an etching process that selectively removes exposed portions of the dummy gate stack without appreciably removing portions of the metallic alloy layer, removing exposed portions of the metallic alloy layer, forming spacers adjacent to the dummy gate stack, forming source and drain regions on exposed regions of the semiconductor fin, removing the dummy gate stack, removing exposed portions of the metallic alloy layer, and forming a gate stack conformally over exposed portions of the insulator layer and the semiconductor fin.

Replacement metal gate FinFET

A structure including a first plurality of fins and a second plurality of fins etched from a semiconductor substrate, and a fill material located above the semiconductor substrate and between the first plurality of fins and the second plurality of fins, the fill material does not contact either the first plurality of fins or the second plurality of fins.

Uniform finFET gate height

A replacement metal gate process which includes forming a fin on a semiconductor substrate; forming a dummy gate structure on the fin; removing the dummy gate structure to leave an opening that is to be filled with a permanent gate structure; depositing a high dielectric constant (high-k) dielectric material in the opening and over the fin; depositing a work function metal in the opening and over the fin so as to be in contact with the high-k dielectric material, the high k dielectric material and the work function metal only partially filling the opening; filling a remainder of the opening with an organic material; etching the organic material until it is partially removed from the opening; etching the work function metal until it is at a same level as the organic material; removing the organic material; and filling the opening with a metal until the opening is completely filled.

A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed.

Structure and method to modulate threshold voltage for high-K metal gate field effect transistors (FETs)

A thin BOX ETSOI device with robust isolation and method of manufacturing. The method includes providing a wafer with at least a pad layer overlying a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer, wherein the first semiconductor layer has a thickness of 10 nm or less. The process continues with etching a shallow trench into the wafer, extending partially into the second semiconductor layer and forming first spacers on the sidewalls of said shallow trench. After spacer formation, the process continues by etching an area directly below and between the first spacers, exposing the underside of the first spacers, forming second spacers covering all exposed portions of the first spacers, wherein the pad oxide layer is removed, and forming a gate structure over the first semiconductor wafer.

Robust isolation for thin-box ETSOI MOSFETS

A method including providing a plurality of fins etched from a semiconductor substrate and covered by an oxide layer and a nitride layer, the oxide layer being located between the plurality of fins and the nitride layer, removing a portion of the plurality of fins to form an opening, and forming a dielectric spacer on a sidewall of the opening. The method may also include filling the opening with a fill material, wherein a top surface of the fill material is substantially flush with a top surface of the nitride layer, removing the nitride layer to form a gap between the plurality of fins and the fill material, wherein the fill material has re-entrant geometry extending over the gap, and removing the re-entrant geometry and causing the gap between the plurality of fins and the fill material to widen.

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Ballston Spa, NY, United States of America

Stefan Schmitz