International Business Machines Corporation

Telefonaktiebolaget Lm Ericsson (publ)

Infineon Technologies Ag

Optis Cellular Technology, LLC

Stefan Sahl

Daniel Joseph Friedman

Alberto Valdes Garcia

Bodhisatwa Sadhu

Scott Kevin Reynolds

Leonard Rexberg

Joakim Hallin

Yahya Mesgarpour Tousi

Jan-Erik Thillberg

Ted Johansson

Hans Norström

Reza Bagger

Örjan Renström

Mats Ernkell

A method and system of a configurable phased array transceiver are provided. A first beamforming unit is configured to provide a first beam. A second beamforming unit is configured to provide a second beam. A first bi-directional power controller is configured to combine or to split the first beam and the second beam. Each beamforming unit comprises a plurality of radio frequency (RF) front-ends, each front-end being configured to transmit and receive RF signals. Each beam is independently configurable to operate in a transmit (TX) or a receive (RX) mode.

Configurable polarimetric phased array transceiver architecture

It is presented a signal generator for providing a first signal on a first output and a second signal on a second output wherein the first signal and the second signal are provided with phase shift relative to each other. The signal generator comprises: a control loop controller; a comparator; a phase shifter, the phase shifter being arranged to provide the first signal on the first output and the second signal on the second output; and a phase error detector, the inputs of which are connected to the outputs of the phase shifter and the output of which is connected to an input of the control loop controller. The output of the control loop controller is connected in a feedback loop to a first input of the comparator, and a second input of the comparator is arranged to be connected to an alternating current source.

Signal generator and associated phase shift apparatus and method

The present invention relates to automatic gain control methods and apparatus for controlling a signal level of a signal at a predetermined location in a signal path of a receiver chain. An automatic gain controller comprises a local signal modifier device for selecting based on an error signal and an oscillator signal from a plurality of alternative oscillator signals, and for providing the selected oscillator signal to a signal mixer located in the receiver chain upstream of said predetermined location for frequency translation of an input signal to said signal mixer.

Method and apparatus relating to signal control

A method in the fabrication of an integrated bipolar circuit for forming a p/n-junction varactor is disclosed. The method featuring the steps of providing a p-doped substrate (); forming a buried n-doped region () in the substrate; forming in the substrate an n-doped region () above the buried n-doped region (); forming field isolation () around the n-doped region (); multiple ion implanting the n-doped region (); forming a p-doped region () on the n-doped region (); forming an n-doped contact region to the buried n-doped region (), the contact region being separated from the n-doped region (); and heat treating the hereby obtained structure to set the doping profiles of the doped regions. The multiple ion implantation of the n-doped region (); the formation of the p-doped region (); and the heat treatment are performed to obtain a hyper-abrupt p/n-junction within the n-doped region ().

Fabrication method, varactor, and integrated circuit

A self-diagnostic asynchronous data buffer includes an addressable buffer having a write address determined by a write counter and a read address determined by a read counter. A write clock controls storage into the buffer and updating of the write counter. A read clock controls reading from the buffer and updating of the read counter. The self-diagnostic asynchronous data buffer additionally has a test register, an address counter, and a state machine. To determine whether a hardware fault exists, the state machine compares the address counter output with the output of the write counter. When the two are equal, the next write to the addressable buffer causes the input data to also be stored in the test register. Next, the address counter output is compared with the output of the read counter. When the two addresses are equal, the output data from the addressable buffer is compared to the value stored in the test register. Inequality between these two values indicates a hardware fault. In an alternative embodiment, a parallel asynchronous data buffer operates by storing into a parity register a parity value of the input data, rather than the input data itself. When the address counter output is equal to the output address of the read counter, parity of the output data from the data buffer is computed and then compared with the value stored in the parity register. Inequality between these two values indicates a hardware fault.

Self-diagnostic data buffers

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Solna, Sweden

Stefan Sahl