Infineon Technologies Ag

Stefan Rueping

Berndt Gammel

Rainer Goettfert

Thomas Nirschl

Gerd Dirscherl

Philip Schlazer

Peter Laackmann

Josef Haid

Ronald Kakoschke

Jan Otterstedt

Marcus Janke

Thomas Leutgeb

Franz Klug

Andreas Wenzel

Dirk Rabe

Kalman Cinkler

A device includes a root of trust and a controller to perform a device function of the device using the root of trust. The root of trust is designed to control and/or observe the controller at least partially for the performance of the device function.

Device and system with a root of trust

A method for data processing including mapping between a logical address and a physical address of a memory, wherein the memory comprises several pages, wherein a group of pages comprises at least one page that comprises at least two portions, and wherein the at least two portions of each page of the group are not part of a single-page logical address space.

Method, device and system for data processing using dedicated mapping between logical and physical addresses

An integrated circuit has one or more logic gates and a control circuit. The control circuit has one or more control elements coupled to the logic gates. The control circuit controls the states of the one or more logic gates.

Integrated circuit and method for manufacturing the same

An apparatus includes a logging apparatus and a configuration apparatus. The logging apparatus has a security module operable to create a manipulation-proof log. The configuration apparatus is operable to configure a configurable microprocessor system. The configuration apparatus is further operable to be coupled to the logging apparatus in order to log a configuration of the microprocessor system using the logging apparatus.

Apparatus for logging a configuration of a microprocessor system and method for logging a configuration of a microprocessor system

A hybrid random number generator (HRNG) including an output, a combinational logic, a TRNG, and a PRNG. The HRNG is configurable to operate in a first and a second mode, wherein in the first mode the PRNG is serially connected between the TRNG and the output and the TRNG intermittently influences the PRNG, and in the second mode the TRNG and the PRNG are connected to the output via the combinational logic.

Hybrid random number generator

An integrated circuit has one or more logic gates and a control circuit. The control circuit has one or more control elements coupled to the logic gates. The control circuit controls the states of the one or more logic gates. The one or more control elements have one or more programmable resistance elements and/or one or more threshold switching elements.

Integrated circuit and method for manufacturing same

An error detection code (EDC) memory module coupled via a bus to a data memory module. In response to a request for data words from a specified memory address within the data memory module, the data memory module provides a predetermined number of data words and the EDC memory module provides a corresponding EDC word.

Error detection code memory module

A system having a pseudo random number generator, a control circuit being configured to increase a quality of a pseudo random number output signal of the pseudo random number generator by coupling the pseudo random number generator with a true random number output signal of a true random number generator and a consumer circuit being configured to use the pseudo random number output signal before and after the increase.

Control of a pseudo random number generator and a consumer circuit coupled thereto

A device for executing a cryptoalgorithm including a central processing unit for a first sub-group of operations and for a flow control of the cryptoalgorithm as well as a hardware circuit for a second sub-group of operations, wherein the first sub-group preferably includes arithmetic and/or logic operations, while the second sub-group includes rotation operations, permutation operations, substitution operations or selection operations.

Device and method for performing a cryptoalgorithm

A circuit arrangement comprising a logic circuit to be tested and a test circuit. The logic circuit comprising logic-circuit-internal combinations configured to generate output data from input data based on a predetermined relationship. The logic circuit is configured to detect whether the relationship is satisfied and to provide an error signal if the relationship is not satisfied. The test circuit is configured to alter logic-circuit-internal combinations, to detect the error signal, and to output an alarm signal if the error signal is not detected upon alteration of the logic-circuit-internal combinations.

Circuit arrangement and method for checking the function of a logic circuit in a circuit arrangement

A semiconductor chip having a subcircuit formed in a substrate; and a phase-change memory cell located on the subcircuit, and configured to directly detect an attack on the subcircuit, or to form a shield to prevent physical access to the subcircuit.

Phase-change memory security device

A memory access controller has a first interface connectable to a memory and a second interface coupled with a first and a second executing unit. A critical software portion is stored in a first segment of the memory, and an uncritical software portion is stored in a second segment of the memory. The critical and uncritical software portions are executed by the first executing unit, and the critical software portion is additionally executed by the second executing unit. The memory access controller further has a first checker having an input for an access request received via the second interface and an output for a first check signal indicating whether the access request is directed to the first segment. Furthermore, the memory access controller has a second checker having an output for a second check signal indicating whether the second executing unit is active, as well as a control unit having inputs for the first and second check signals and an output for an alarm signal indicating that the access request is directed to the first segment and the second executing unit is not active.

Memory access controller and method for memory access control

An apparatus and method of accessing a memory by determining available power, and accessing a number of bits of the memory in parallel, wherein the number of bits accessed in parallel is based at least in part on the available power.

Power dependent memory access

A bit sequence which is generated by a feedback shift register is decimated with a variable decimation value m (m&#x3b5;|N) in a predetermined manner which is known on the decryption side, i.e. in that every mbit of the bit sequence is picked out from the bit sequence so as to obtain the key bit stream.

Key bit stream generation

Feedback shift register control circuit including a checking circuit having an input being coupled to a seed input of a feedback shift register or to an internal node of the feedback shift register, the checking circuit configured to be responsive to a signal at the input indicating that the feedback shift register is in a not-allowed state, or is going to assume a not-allowed state to output an exception signal; and a gate circuit being coupled to the seed input or the feedback shift register and configured to be responsive to the exception signal to change the state of the feedback shift register or seed the feedback shift register such that the feedback shift register assumes an allowed state.

Growing community of inventors

Lengdorf, Germany

Stefan Rueping