Texas Instruments Corporation

Texas Instruments Incorporated Deutschland, Gmbh

Stefan Reithmaier

Erich Bayer

Kevin Scoones

Carsten Stoerk

Nigel Peter Smith

Josy Bernard

Laszlo Goetz

Byoung-Suk Kim

Nicolas M Guibourg

Gerhard Thiele

Franz Prexl

Nicola Rasera

Ivan Shumkov

Johann Erich Bayer

Juergen Neuhaeusler

Christian Harder

Roland Bucksch

Martin Rommel

Rüdiger Ganz

Markus Georg Rommel

Niko Bako

Christian Rott

Florian Neveu

Laszio Goetz

A buck-boost converter includes a voltage input terminal, a voltage output terminal, a first switch, a second switch, an inductor, a third switch, and an auxiliary capacitor. The first switch includes a first terminal coupled to the voltage input terminal, and a second terminal. The second switch includes a first terminal coupled to the voltage output terminal, and a second terminal. The inductor is coupled between the second terminal of the first switch and the second terminal of the second switch. The third switch includes a first terminal coupled to the second terminal of the second switch, and a second terminal. The auxiliary capacitor is coupled to the second terminal of the third switch.

Single inductor buck-boost converter with auxiliary capacitor

A circuit includes a binary weighted divider having a first set of switches coupled in series between an input node and a feedback node. The first set of switches is configured to set a feedback voltage at the feedback node in response to activating or deactivating respective switches in the first set of switches. A set of compensation switches is coupled to the first set of switches. The set of compensation switches is configured to reduce resistance of one or more of the respective switches in the first set of switches that are activated by activating one or more switches in the set of compensation switches to provide one or more respective parallel current paths for each of the switches in the first set of switches that are activated.

Compensation for binary weighted divider

In an example, a dual-phase inverting buck-boost power converter for use with at least first and second energy storage elements includes an inverting buck-boost power converter and an inverting boost converter. In an example, the inverting buck-boost power converter is coupled between an input node and an output node of the dual-phase inverting buck-boost power converter and includes a first plurality of switches operable to couple to the first energy storage element, wherein the inverting buck-boost power converter is operable to supply a first load current. In an example, the inverting boost converter is coupled in parallel with the inverting buck-boost power converter between the input node and the output node of the dual-phase inverting buck-boost power converter and includes a second plurality of switches operable to couple to the first and the second energy storage elements, wherein the inverting boost converter is operable to supply a second load current.

Inverting buck-boost power converter

A circuit includes a signal generator to generate an output signal to vary the switching frequency of a switching circuit to mitigate noise in the switching circuit. The signal generator includes a modulation waveform generator (MWG) to generate a ramp signal in response to a numerical input and a switching signal from the switching circuit. The ramp signal is employed to modulate the frequency of the output signal of the signal generator over a range of frequencies from a minimum frequency to a maximum frequency. A frequency adjuster circuit modulates the amplitude of the ramp signal by adjusting at least one of the minimum frequency or the maximum frequency of the range of frequencies.

Spectrum modulation for switching circuits

A level shifter circuit has a plurality of channels for providing signals to a capacitive load and has circuits for sharing charge stored in the capacitive load between the channels. A first pair of channel clock generating circuits are coupled respectively to a first pair of channels. A second pair of channel clock generating circuits are coupled respectively to a second pair of channels. A pair of switches couple the first pair of channels together and the second pair of channels together, respectively, for sharing charge between the channels. A single resistor is coupled in circuit with all of the channels for controlling a slope of charge sharing between channels.

Cost effective low pin/ball count level-shifter for LCD bias applications supporting charge sharing of gate lines with perfect waveform matching

An electronic device comprising a level shifter and a method. The level shifter includes an input adapted to receive an input signal switching between a low input voltage level and a high input voltage level and a first switch and a second switch coupled in series between a low output voltage supply and a high output voltage supply. An output is coupled to an interconnection node between the first and the second switch and is adapted to be coupled to a load. The first and second switches are controlled by the input signal. The level shifter further includes a third switch which is coupled between the interconnection node and an auxiliary voltage supply which has a voltage level between the low output voltage level and the high output voltage level.

Electronic device and method for providing a digital signal at a level shifter output

A level shifter for use in LCD display applications is provided which includes a group of separate channels each with a signal input and a signal output and with channel control circuitry supporting gate voltage shaping for improving image quality. The level shifter further has a number of flicker clock inputs. The channel control circuitry of each particular channel in the group comprises logic circuitry combining all of said flicker clock inputs with the signal input of the particular channel and signal inputs form other channels into a gate voltage shaping enable signal for the control circuitry of the particular channel. With this configuration it is possible to use the same level shifter IC with only one flicker clock signal for all phases, regardless of how many, without the need for an additional synchronization signal, or multiple flicker clock signals as is conventional. The level shifter automatically determines which input signal needs to be modified for the gate voltage shaping when the active portion of the flicker clock signal is detected.

Level shifter for use in LCD display applications

A converter has a single inductor with a first terminal connectable to a first terminal of the supply input through a first power transistor and a second terminal connectable to a second terminal of the supply input through a second power transistor. A first rectifier element connects the first terminal of the inductor with a first output terminal, and a second rectifier element connects the second terminal of the inductor with a second output terminal. A resistive voltage divider is connected between the first and second output terminals. A control circuit uses an input from the voltage divider as a reference input voltage and provides an output current to the second terminal of the supply input in response to any voltage difference between the reference input voltage and the second terminal of the supply input. This provides a virtual common reference potential at the second terminal of the supply input, which is thus a common ground (GND) terminal. In the ON phase of both power transistors, the inductor is charged with current from the supply input. In the OFF phase (both power transistors are OFF), the energy stored in the inductor is supplied to both of the positive and the negative supply output through the rectifier elements, the output current in fact flowing almost exclusively between the positive and negative supply outputs. Thus, in the OFF phase, the inductor is entirely isolated from the supply input and the supply outputs are in no way affected by any transients or fluctuations in the supply input voltage.

DC-DC converter usable for dual voltage supply

A control circuit for a polarity inverting buck-boost DC-DC converter, includes an operational trans-conductance amplifier that has inputs to which a sensed voltage difference signal is applied and an output connected to an input of a voltage-to-duty-cycle converter. A compensation capacitance is connected between the output of the amplifier and a fixed supply terminal. The compensation capacitance includes a first capacitor that is permanently connected between the output of the amplifier and the fixed supply terminal and a second capacitor that has a switched connection between the output of the amplifier and the fixed supply terminal. The first capacitor has a small capacitance compared to the second capacitor. The switched connection of the second capacitor is controlled by a continuous-discontinuous mode detection circuit.

Control circuit for a polarity inverting buck-boost DC-DC converter

A DC-DC high frequency boost converter with a supply voltage input (), a boosted voltage output (), a series circuit of an inductor () and a rectifying device () connected in series between said supply voltage input () and said boosted voltage output (), has a switch () connected between ground and a connection node () of said inductor () and said rectifying device (). A control circuit () is provided for controlling said switch (), and a zero inductor current detection circuit () is provided that compares a voltage (U) on said connection node () with a reference voltage (U) and provides a zero inductor current indication (Comp) when both voltages are equal.

DC-DC high frequency boost converter

The invention relates to a reference voltage source including a bipolar transistor having a base, a collector and an emitter electrode. The reference voltage source further comprises a Schottky diode (D) whose anode is connected to the base electrode of the bipolar transistor and whose cathode is connected to the collector electrode of the bipolar transistor. The currents flowing through the Schottky diode and bipolar transistor are each set so that a temperature-independent reference voltage (VREF) materializes at the collector electrode of the bipolar transistor.

Reference voltage source

A comparator includes a differential amplifier stage comprising two emitter-interconnected bipolar transistors whose bases form the two inputs of the comparator, a first load element connected to the collector of the first bipolar transistor and a second load element connected to the collector of the second bipolar transistor. The comparator also includes a first MOSFET and a second MOSFET, a circuit point at which the drop in voltage across the first load element in operation of the differential amplifier stage occurs is connected to the source of the first MOSFET and the backgate of the second MOSFET, the circuit point at which the drop in voltage across the second load element in operation of the differential amplifier stage being connected to the source of the second MOSFET and the backgate of the first MOSFET, and the drain of the second MOSFET forming the output of the comparator. The comparator, in addition to providing the low offset voltage of a differential amplifier stage comprising bipolar transistors, also features a low current consumption and very fast response.

Comparator

The circuit configuration for the generation of a reference voltage (Vref) contains a reference voltage source ( ) and a storage capacitor (C ) to which a voltage provided by a reference voltage source ( ) can be applied via a controllable switch. The charging voltage of this storage capacitor (C ) is the reference voltage to be generated. The controllable switch (P ) is a MOS field-effect transistor with back gate ( ) which, by means of a refresh signal supplied by a control circuit ( ), can be put periodically into either a conducting or a non-conducting state. The back gate ( ) of the MOS fieldeffect transistor (P ) is connected to an auxiliary storage capacitor (C ) to which the voltage supplied by the reference voltage source ( ) can be applied via a further switch, consisting of a MOS field-effect transistor (P ) with back gate ( ), and which is also controlled by the refresh signal. The back gate ( ) of the further MOS field-effect transistor (P ) is connected to a fixed voltage, which is greater than the voltage supplied by the reference voltage source ( ).

Circuit configuration for the generation of a reference voltage

A digital driver circuit with one or more CMOS inverters intended as input stages, whereby for the MOS FETs of the inverters the channel width/length (W/L) ratio increases from stage to stage. The digital driver circuit includes an intermediate stage with two further CMOS inverters, connected between a supply voltage Vcc and ground. The driver circuit also includes an output stage having two MOS FETs with the drain terminals of both the MOS FETs of the output stage connected both to each other and to the output of the circuit, the W/L ratio of both MOS FETs exceeding that of the MOS FETs of the intermediate stage. The switch-over of the two MOS FETs of the output stage, occurring with changes of the digital input signal at the input of the circuit, is offset in time with respect to each other, thereby reducing current peaks.

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Vilsheim, Germany

Stefan Reithmaier