Infineon Technologies Ag

Siemens Aktiengesellschaft

Infineon Technologies LLC

Stefan Pfab

Holger Sedlak

Albrecht Mayer

Michael Baldischweiler

Martin Kaibel

Klaus Oberl&auml;nder

Klaus Oberlander

The program-controlled unit, during the execution of the program, can switch itself to a state in which selected elements that can be connected to form scan chains or all of the elements can no longer change their state, according to a predetermined result. If these elements are then connected to form a scan chain and read out, the data obtained as a result can be used to identify and/or analyze any errors existing in the program-controlled unit rapidly and reliably.

Program-controlled unit and method for identifying and/or analyzing errors in program-controlled units

A data storage device is disclosed that, in response to a data output request, outputs stored data beginning with a selected output start address. The disclosed data storage device is characterized in that the selectable output start addresses exhibit such slight spacings from one another that the amount of data storable between neighboring output start addresses is smaller than the amount of data output in response to a data output request. As a result thereof, the plurality of accesses onto the data storage device can be reduced to a minimum.

Data storage device with overlapped buffering scheme

The microprocessor device has a central processing unit in which the instructions that are stored in a program memory are converted into arithmetic or logical combinations for controlling the different components of the microprocessor. A data and/or control line bus enables data transfer and access to CPU-internal and/or peripheral-bound special function registers, which are assigned to the central processing unit. A coherent memory block with memory cells of the random access type is assigned to the central processing unit through the data and/or control line bus. The memory block has a dedicated address decoder and bus driver circuit, and has a first, arbitrarily usable and/or accessible memory area and a second, peripheral-independent and directly addressable memory area. The memory block is assigned an enable device which disables or enables the output of data contents from the second memory area onto the data and/or control line bus.

Microprocessor device

The method described is distinguished in that overwriting return addresses stored for later use and/or using incorrectly stored or overwritten return addresses as a return address are prevented. This further prevents deliberate manipulation of program execution of software programs.

Method of monitoring the correct execution of software programs

An electronic data processing circuit includes an operating module such as a microprocessor, at least one data memory and a data bus extending between the data memory and the operating module. In order to provide an electronic data processing circuit which is better protected against undesired alterations, at least one encoding module is provided in the region between the data memory and the data bus and/or in the region between the operating module and the data bus. The encoding module is constructed in such a way that data traffic between the operating module and the data bus or between the data memory and the data bus can be encoded and/or decoded.

Electronic data processing circuit

A circuit configuration having a number of electronic circuit components. The operating state of the circuit components can be set to a reset or erase state by a predetermined control signal applied to the respective circuit component in which state a data content of the circuit component assumes a logic zero value. For the purpose of chronologically successive resetting the data contents of all the circuit components, a selection circuit is provided which is activated to allow the writing of the logic zero value to the circuit components. The selection circuit has a number of opening stages corresponding to the number of circuit components. The opening stages are connected in series one after the other and each circuit component is respectively assigned an opening stage of the selection circuit. Each opening stage with the exception of the first opening stage is activated or driven by an opening signal which is generated by the immediately preceding opening stage, for the purpose of outputting a control signal to the associated circuit component. Following the resetting of the associated circuit component, the opening stage in turn outputs an opening signal for the purpose of driving or activating an immediately succeeding opening stage.

Growing community of inventors

Grosshesselohe, Germany

Stefan Pfab