Cypress Semiconductor Corporation

Nvidia Corporation

Lara Technology, Inc.

Stefan P Sywyk

Andrew L Hawkins

Eric H Voelkel

Richard K Chou

Jesse S Wang

Lalit Gupta

Andreas J Gotterba

Raymond E Bloker

Sow T Chu

The disclosure introduces a level-shifter including a boost circuit that provides a 'one-shot' pulse (a self-annihilating pulse) with the transitioning edge of the output signal. The pulse can be used to produce a faster output rise time and reduce the overall footprint of a level-shifter compared to conventional level-shifters. In one example the level-shifter includes: (1) input circuitry configured to receive one or more input signals from one or more input voltage domains, (2) output circuitry configured to provide an output signal, based on at least one of the one or more input signals, for an output voltage domain, wherein an operating voltage of the output voltage domain is greater than an operating voltage of the one or more input voltage domains, and (3) a boost circuit connected to the output circuitry and configured to provide a current pulse for a transition edge of the output signal.

Level-shifter having a wide operating range, a fast output fall delay and improved rise time

A static random access memory (SRAM) or other bit-storing cell arrangement includes memory cells and a hierarchical bitline structure including local bitlines for subsets of the memory banks and a global bitline spanning the subsets. A keeper circuit for the global bitline is replaced by bias circuitry on output transistors of the memory cells.

Keeper-free volatile memory system

A machine memory includes multiple memory cells. Word lines, each with at least one word line driver, are coupled to the memory cells along rows. The word line drivers of at least some adjacent pairs of the word lines are coupled together by a pull-down transistor, in a manner that reduces read disturb of the memory cells.

Area efficient memory cell read disturb mitigation

According to one embodiment, a timing circuit () can include a first control circuit (), a first clocked circuit (), a second clocked circuit (), and a second control circuit (). A first control circuit () may compensate for a first timing signal FCLK making a transition earlier in time than a second timing signal RCLK. A second control circuit () may compensate for a second timing signal RCLK making a transition earlier in time than a first timing signal FCLK. A first timing signal FCLK can be a periodic signal generated by a first PLL type circuit () in response to a falling edge of an external clock signal EXT CLK. A second timing signal RCLK can be a periodic signal generated by a second PLL type circuit () in response to a rising edge of an external clock signal EXT CLK.

Timing method and apparatus for integrated circuit device

According to one embodiment, a content addressable memory (CAM) ( ) can include a number of ordinary rows ( - to -n) that provide ordinary match indications (Match to Matchn) as well as redundant rows ( - and - ) that can provide redundant match indications (RMatch and RMatch ). If an ordinary row ( - to -n) is defective, a redundancy multiplexer ( - to -n) can be switched to provide a redundant match indication (RMatch and RMatch ) as an input to a priority encoder ( ) instead of the ordinary match indication from the defective ordinary row.

Content addressable memory having redundancy capabilities

In a single ended simplex dual port memory cell, one port of the memory cell is dedicated for writing operations and the other port of the memory cell is dedicated for reading operations. A bit of data received from the first port can be stored in the memory cell. The second port can detect the memory cell contents substantially simultaneously as the memory cell is storing a bit of data from the first port. Each port is optimized for its respective dedicated operation. In other words, one port is optimized for write operations and the other port is optimized for read operations. Because one port of the memory cell is optimized for write operations and the other port of the memory cell is optimized for read operations, the cell does not require multiple wordline voltages for each port.

Single ended simplex dual port memory cell

A content addressable memory (CAM) ( ) can include a number of CAM entries ( - to -n). Match indications from CAM entries ( - to -n) and mismatch indications from complementing circuits ( - and -n) can be supplied to a switching circuit ( ). Mismatch indications can indicate if an entry mismatches data when compared with a comparand ( ). In one mode of operation, a switching circuit ( ) can provide match indications on a number of switch outputs (SW to SWn). In another mode of operation, switching circuit ( ) can provide mismatch indications on a number of switch outputs (SW to SWn).

Method and apparatus for content addressable memory test mode

According to one embodiment, the write circuitry of a content addressable memory (CAM) can include periphery circuits ( ) that generate data signals ( ) and write control signals ( ) that connect over some distance to CAM core circuits ( ). CAM core circuits ( ) may include bitline write driver circuits ( ), a write control circuit ( ), and CAM cells ( ). Write control signals ( ) may include a signal surrounded by its complements and be positioned such that a routing of the write control signal is as long as the longest of the data signals ( ).

Write method and circuit for content addressable memory

According to one embodiment, a content addressable memory (CAM) ( ) can include a number of CAM entries ( - to -n) and corresponding status stores ( - and -n). Match indications from the CAM entries ( - to -n) and status information from status stores ( - and -n) can be supplied to a switching circuit ( ). Status information can indicate if an entry stores valid or invalid data. In one mode of operation, the switching circuit ( ) can provide match indication values on a number of switch outputs (SW to SWn). In another mode of operation, the switching circuit ( ) can provide status information on a number of switch outputs (SW to SWn).

Content addressable memory having prioritization of unoccupied entries

According to one embodiment, a content addressable memory (CAM) can include at least one match line ( ), series-coupled transistor pairs comprising match transistors ( - to -n) and switch devices ( - to -n), bit match indicator signals ( - to -n), mask cell value signals ( - to -n), a match line precharge limiting device ( ), a match line precharge control device ( ) and an amplifier circuit ( ). This configuration can allow for the regulation of the match line ( ) discharge path through a discharge control device ( ) and a match indication feedback device ( ). This, in turn, can allow for match line ( ) precharging while at least one of the bit match indicator signals ( - to -n) is in an intermediate, or approximately half-VDD, level that is consistent with relatively low power precharging of the applied comparands. As such, the pseudo-VSS ( ) line control may prevent a static current path from developing during the precharge scenario described above by directly controlling the path between the pseudo-VSS ( ) line and the circuit ground supply.

Content addressable memory having reduced current consumption

A single ended simplex dual port memory cell is described. One port of the memory cell is dedicated for writing operations and the other port of the memory cell is dedicated for reading operations. A bit of data received from the first port can be stored in the memory cell. The second port can detect the memory cell contents substantially simultaneously as the memory cell is storing a bit of data from the first port. Each port is optimized for its respective dedicated operation. In other words, one port is optimized for write operations and the other port is optimized for read operations. Because one port of the memory cell is optimized for write operations and the other port of the memory cell is optimized for read operations, the cell does not require multiple wordline voltages for each port.

According to one embodiment a content addressable memory (CAM) (,) can segment comparand values and data values into portions. Comparand value portions are compared with corresponding data value portions in sequential compare operations. Sequential compare operations can distribute current peaks over two or more compare operations, thereby reducing peak current transients.

Content addressable memory with reduced transient current

According to one embodiment, a multiple signal detect circuit (,) can include a detect node (,) and a reference node (,). The potential of the detect node (,) can be discharged (or charged) at a rate that depends upon the number of active input signals (M,to Mn). The potential of the reference node (,) can be discharged (or charged) at a reference rate. The reference rate can be greater than the rate at which the detect node (,) is discharged (or charged) when one input signal is activated, and less than the rate at which the detect node (,) is discharged (or charged) when two input signals are activated. A differential voltage between the detect node (,) and reference node (,) can be amplified by an amplifier (,).

Multiple signal detection circuit

A method of reading the contents of a dual port memory cell which has a Beta Ratio less than 1.5 is described. A wordline is associated with a selected port of the memory cell. The wordline is coupled to a gate device of the memory cell for controlling communication between the memory cell and a bitline. The gate device has a first conductance at a first wordline voltage and a second conductance at a second wordline voltage. The second conductance is less than the first conductance. A port of the cell is selected by applying a select voltage to the associated wordline. The select voltage is approximately the same as the second wordline voltage. The cell contents are then retrieved from the bitline.

Single ended dual port memory cell

A single ended dual port memory cell is described. A bit of data received from one of the first and second ports can be stored. Each of the first and second ports can simultaneously detect the stored bit. A method of reading the contents of a dual port memory cell which has a Beta Ratio less than 1.5 is also described. A wordline is associated with a selected port of the memory cell. The wordline is coupled to a gate device of the memory cell for controlling communication between the memory cell and a bitline. The gate device has a first conductance at a first wordline voltage and a second conductance at a second wordline voltage. The second conductance is less than the first conductance. A port of the cell is selected by applying a select voltage to the associated wordline. The select voltage is approximately the same as the second wordline voltage. The cell contents are then retrieved from the bitline.

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San Jose, CA, United States of America

Stefan P Sywyk