International Business Machines Corporation

Stefan P Jackowski

James Wilson Bishop

Gregory Robert Klouda

James T Moyer

Ronald B Jenkins

Robert D Siegl

Phillip G Williams

Timothy Carl Bronson

Patrick W Gallagher

Charles Embrey Carmack, Jr

William Eric Hall

Bruce Leroy Beukema

Ronald Edward Fuhs

Eric M Foster

Glenn David Gilda

Anthony J Bybell

Dennis E Franklin

William Garrett Verdoorn, Jr

Mark J Wolski

David Wallach

David N Gooding

Mark Louis Ciacelli

John M Sheplock

Peter N James

James W Plant

Richard L Hester

Robert G Rush

Gregory S Ulsh

Patrick Wayne Gallagher

A circuit arrangement, method, and design structure for controlling access to master secret data disposed in at least a portion of at least one persistent region of an integrated circuit device is disclosed. The circuit arrangement includes a clock circuit responsive to an external clock signal, a security state machine configured to control a security state of the integrated circuit device, and a master secret circuit in communication with the security state machine and configured to control access to the master secret data. The security state machine and master secret circuit are isolated from the clock circuit, and the master secret circuit is responsive to the security state machine to selectively erase at least a portion of the master secret data. The master secret circuit may be configured to erase the portion of the master secret data in response to a null or triggered security state.

Protecting isolated secret data of integrated circuit devices

An opaque memory region for a bridge of an I/O adapter. The opaque memory region is inaccessible to memory transactions which traverse the bridge either from a primary bus to secondary bus or secondary bus to primary bus. As a result, memory transactions which target the opaque memory region are ignored by the bridge, allowing for the same address to exist on both sides of the bridge with different data stored in each. The implementation of the opaque memory region provides a means to complete memory transactions within I/O adapter subsystem memory, hence, relieving host computer system memory resources. In addition, a number of I/O adapters can be used in a host computer system where the host and all the I/O devices use some of the same memory addresses.

Opaque memory region for I/O adapter transparent bridge

Dynamic routing of data to multiple processor complexes. PCI address space is subdivided among a plurality of processor complexes. Translation table entries at each processor complex determine which processor complex is to receive a DMA transfer, thereby enabling routing of DMA data to one I/O hub node while accessing translation table entries at another I/O hub node. Further, interrupt requests may be dynamically routed to multiple processor complexes.

System and method for supporting access to multiple I/O hub nodes in a host bridge

A multi-path access control device for an integrated system is presented which allows simultaneous access to multiple external devices coupled thereto by multiple functional units. The multiple functional units are coupled to the shared access control device across two or more high speed, shared data buses. The control device includes multiple bus ports, each coupled to a different data bus, and a non-blocking crossbar switch coupled to the bus ports for controlling forwarding, with zero cycle latency, of requests from the functional units. Multiple external device ports are coupled to the non-blocking crossbar switch for receiving requests forwarded by the crossbar switch, and each external device is coupled to a different external device port. The crossbar switch allows multiple requests at the bus ports directed to different external devices to be forwarded to different external device ports for simultaneous accessing of different external devices coupled thereto pursuant to the multiple requests.

Shared access control device for integrated system with multiple

A hierarchical cache system comprises first and second pluralities of data caches and first and second respective higher level caches. The first higher level cache is coupled to the first plurality of caches and stores data of the first plurality of caches. The second higher level cache is coupled to the second plurality of caches and stores data of the second plurality of caches. First and second storage controllers access first and second respective address ranges from a main memory and the higher level cache subsystems. The first higher level cache responds to a request for data not contained in the first higher level cache by determining which of the address ranges encompasses the requested data and forwarding the request to the storage controller which can access the determined address range. The second higher level cache responds to a request for data not contained in the second higher level cache by determining which of the address ranges encompasses the requested data and forwarding the request to the storage controller which can access the determined address range.

Multi-level computer cache system providing plural cache controllers

In a hierarchical, multi-level storage system, recovery from intermittent storage hardware failures is supported by establishing hardware checkpoints at storage system interfaces and by duplication of subsystem hardware within units of the storage system. When error is detected at an interface, all levels of the storage system are quiesced and backed up to a point preceding the occurrence of the error. If a hardware failure causes an error, the system is quiesced while the failed hardware is reconfigured with control logic copied from duplicate hardware. A single restart command restarts system operation.

Error windowing for storage subsystem recovery

A hierarchical cache system comprises a plurality of first level cache subsystems for storing data or instructions of respective CPUs, a higher level cache subsystem containing data or instructions of the plurality of cache subsystems, and a main memory coupled to the higher level cache subsystem. A page mover is coupled to the higher level cache subsystem and main memory, and responds to a request from one of the CPUs to store data into the main memory, by storing the data into the main memory without copying previous contents of a store-to address of the request to the higher level cache subsystem in response to said request. Also, the page mover invalidates the previous contents in the higher level cache subsystem if already resident there when the CPU made the request. A buffering system within the page mover comprises request buffers and data segment buffers to store a segment of predetermined size of the data. When all of the request buffers have like priority and there are fewer request buffers that contain respective, outstanding requests than the number of data segment buffers, the page mover means allocates to the request buffers with outstanding requests use of the data segment buffers for which there are no outstanding requests.

Hierarchical computer cache system

The I/O configuration of a computer system includes two channels which are capable of being available on up to four interface ports, with the ports being incorporated within the channel in order to eliminate the need for an external switch. Control indicators are provided for monitoring the communications request initiation status of each channel and each port to achieve expeditious transfers through a selected port between the channel and peripheral devices. The I/O configuration is established responsive to the communications request initiation status that indicates one of several states depending on which side initiates a request and whether the connection has been made.

System for controlling multiple port/multiple channel I/O configuration

The I/O configuration of a computer system includes two channels which are capable of being available on up to four interface ports, with the ports being incorporated within the channel in order to eliminate the need for an external switch. Control means are provided for monitoring the status of each channel and each port in order to achieve expeditious transfers through a selected port between the channel and peripheral devices. Error reporting is limited to the area directly affected by the error, and immediate disconnection helps to isolate the error and allow time for error recovery before the particular channel or port again becomes available.

Error recovery in a multiple 170 channel computer system

A system structured to transfer control information between an IFA (I/O interface adapter) and an I/O processor, and I/O data between an IFA and a CDB (channel data buffer) has separate interfaces for these transfers. The control interface includes a multi-mode, bidirectional control data bus, a control mode bus for establishing the mode of the bus, and a check interface on which the IFA provides error information. The data interface includes a multi-mode, bidirectional data transfer bus, respective SYNC and ACCEPT lines for transferring time-phased control signals to establish the mode of the data transfer bus, and a parity line to indicate to the IFA the parity of the SYNC and ACCEPT lines.

Multimode data system for transferring control and data information in

A system for ensuring accurate transmission of data between two functional units. A checking code generator is provided and a device operatively connected to the checking code generator ensures proper operation thereof.

Device for verifying operation of a checking code generator

A failure detection apparatus detects the existence of an abnormal circuit condition in a circuit which causes a subsequently transmitted data byte to be transmitted from one integrated circuit to another integrated circuit out of sequence relative to a previously transmitted data byte. Even and odd data bytes are received by the first integrated circuit with odd parity. However, the even data byte is transmitted from the first integrated circuit to the second integrated circuit, along existing interface lines extending between the integrated circuits, with odd parity. The parity bit of the odd data byte is inverted, the odd data byte being transmitted along the existing interface lines with even parity. An exclusive OR gate in the second integrated circuit receives the parity bit of the even data byte and passes the parity bit without inversion in response to a first state of a clock signal from an odd latch; however, the exclusive OR gate, upon receipt of the odd data byte, re-inverts the parity bit of the odd data byte in response to a second state of the clock signal. A parity checker compares the data bits of the incoming even and odd data bytes with the parity bit generated by the exclusive OR gate and generates an error check signal representative of the receipt of the subsequently transmitted data byte transmitted out of sequence relative to the previously transmitted data byte when the combined parity of the data bits and parity bit at the input of the parity checker is not odd.

Failure detection method and apparatus

Interface lines interconnect a first circuit to a second circuit. When an abnormal circuit condition affects the interface lines, such as an open circuit or a short circuit condition, the operation of the first and second circuit is detrimentally affected. This invention determines the existence of abnormal circuit conditions in one or more lines of a group of interface lines without using redundant duplex lines. The interface lines are subdivided into a first group, which are used when the apparatus of the present invention is being used to locate abnormal circuit conditions, and a second group, which are not used when the apparatus of the present invention is being used to locate abnormal circuit conditions. Each line of the first group is connected, at its input side, to a corresponding input terminal of a first exclusive-or gate and, at its output side, to a corresponding input terminal of a second exclusive-or gate. The first and second exclusive-or gates are input to a matching circuit, an output signal from the matching circuit indicating the existence of an abnormal circuit condition in the first group of lines. One line of the first group is connected to an input side of the second group. The output side of the second group is connected to an additional input terminal of the second exclusive-or gate. An output signal from the matching circuit indicates the existence of an abnormal circuit condition in at least one line of either one or both of the first and second group of lines.

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Endicott, NY, United States of America

Stefan P Jackowski