Vlsi Technology, Inc.

Koninklijke Philips Corporation N.V.

Stefan Ott

A clock synchronization system for synchronizing a first communications device and a second communications device to enable digital communication there between. A first device generates a first clock signal Fa. A second device generates a second clock signal Fb . The second device includes a first PLL circuit and a second PLL circuit. The first PLL circuit is adapted to increase Fa by a factor K to produce a signal Fak. The second PLL circuit is adapted to increase Fak by a factor L to produce a signal Fbn. The second PLL circuit is further adapted to decrease Fbn by a factor N to produce the signal Fb . The first PLL circuit and the second PLL circuit are adapted to adjust the values of K, L, and N such that a frequency lock is achieved between Fa and Fb . enabling digital communication between the first device and the second device without requiring a predetermined phase lock between Fa and Fb

Cascading PLL units for achieving rapid synchronization between digital communications systems

A dynamic error correction system for a digital data transmission system. A transmitter adapted to encode user data into a signal is included within the system. A receiver receives the signal and decodes the user data encoded thereon. The signal is transmitted from the transmitter to the receiver via a communications channel. A data type detector is coupled to the transmitter. The data type detector is adapted to detect a data type of the user data being coupled to the transmitter for transmission via the communications channel. A processor is coupled to the transmitter and is adapted to implement at least a first error correction process and a second error correction process for the transmitter, wherein the second error correction process is of a higher capability than the first error correction process. The processor is coupled to receive the data type from the data type detector and dynamically select the first error correction process or the second error correction process in response thereto such that error correction employed by the transmitter is best suited to the data type of the user data.

Method and system for detecting user data types in digital communications channels and optimizing encoding-error correction in response thereto

A system to avoid unstable data transfer between digital systems. The present invention includes a system that enables digital systems to communicate while avoiding unstable data transfer, which can result in a loss of data or signal distortion. For instance, the present invention includes a system that enables detection of potentially unstable operating conditions for a digital receiver device during its reception of clock and digital data signals from a digital transmitter device. One embodiment of the present invention monitors the received clock and digital data signals in order to detect any potential violations of the internal input timing requirement of the digital receiver device. If any potential violations of the input timing requirement are detected, the present invention invokes measures to eliminate them by manipulating the phase of the clock signal utilized internally by the digital receiver device to sample the received digital data signals. In this manner, the present invention ensures that the digital receiver device internally operates within its input timing requirement and thereby avoids unstable operating conditions which can result in signal distortion or a loss of data. Therefore, the present invention enables digital systems to communicate while avoiding unstable data transfer.

System to avoid unstable data transfer between digital systems

A dynamic error correction system for a bi-directional digital data transmission system. The transmission system of the present invention includes a transmitter adapted to encode information into a signal. A receiver receives the signal and decodes the information encoded thereon. The signal is transmitted from the transmitter to the receiver via a communications channel. A signal quality/error rate detector is coupled to the receiver and is adapted to detect a signal quality and/or an error rate in the information transmitted from the transmitter. The receiver is adapted to implement at least a first and second error correction process, depending upon the detected signal quality/error rate. The first error correction process is more robust and more capable than the second error correction process. The receiver coordinates the implemented error correction process with the transmitter via a feedback channel. The receiver dynamically selects the first or second error correction process for implementation in response to the detected signal quality/error rate and coordinates the selection with the transmitter such that error correction employed by the receiver and transmitter is tailored to the condition of the communications channel.

Smart dynamic selection of error correction methods for DECT based data services

A clock synchronization circuit for synchronizing a first communications device and a second communications device to enable digital communication between the devices. The clock synchronization circuit includes an oscillator circuit adapted to generate a base clock signal. A first frequency divider is coupled to the oscillator circuit. The first frequency divider generates a first divider clock signal from the base clock signal. A phase comparison circuit is coupled to receive the first divider clock signal. Additionally, the phase comparison circuit is also coupled to the oscillator circuit to control the frequency of the base clock signal. The phase comparison circuit receives a reference clock signal from a first communications device and adjusts the base clock frequency to correct a phase difference between the first divider clock signal and the reference clock signal. The clock synchronization circuit further includes a second frequency divider coupled to the oscillator circuit. The second frequency divider is adapted to generate a second divider clock signal from the base clock signal, wherein the second divider clock signal varies in response to the correcting performed on the base clock signal by the phase comparison circuit. The second frequency divider subsequently provides the second divider clock signal to a second communications device such that the first communications device and the second communications device are synchronized.

Method and system for rapidly achieving synchronization between digital

The present invention comprises a sample rate conversion system for eliminating sample rate slippage. The system of the present invention includes a first sample rate conversion circuit and a second sample rate conversion circuit. The first sample rate conversion circuit is adapted to multiply a sample rate frequency by a factor 'N', producing a first converted sample rate frequency. The a second sample rate conversion circuit is adapted to divide the first converted sample rate frequency by a factor of 'M', producing a second converted sample rate frequency. The sample rate frequency is used to encode an input signal, producing an encoded signal. The second converted sample rate frequency is used to decode the encoded signal, producing an output signal. The second converted sample rate frequency and the values of N and M are adjusted such that the input signal is substantially the same as the output signal, eliminating sample rate slippage.

Receiver sample rate frequency adjustment for sample rate conversion

The present invention comprises a system for efficiently using non-volatile memory in an embedded system. The system of the present invention includes an embedded system having a processor, a volatile memory, and a non-volatile memory. A decompression algorithm is stored in the non-volatile memory along with a main program. When the embedded system is powered up, the decompression algorithm is executed by the processor. The decompression algorithm operates on compressed software stored in the non-volatile memory. The compressed software includes data needed to initialize the main program. After the operation of the algorithm, the decompressed software is loaded into the volatile memory, thereby initializing the main program. Since the software for initializing the main program is stored in non-volatile memory in a compressed state, and since the decompression algorithm is compact, the present invention efficiently utilizes non-volatile memory space.

Method and system for using decompression on compressed software stored

A method and implementing system includes transmitting a sampled and digitized source analog signal which is sampled for transmission at a rate of FT, to a receiving device and converting the received signal by a first sample rate converter circuit which is effective to multiply the sample rate FT by a first factor 'N'. The converted signal is then processed by a receiver sampler circuit and applied to a second sample rate converter circuit operating at a rate of a receiver frequency FR. The second sample rate converter circuit is effective to divide the processed signal by a second factor 'M'. The signal is then processed by a digital to analog converter and filtered to filter out the spurious components and provide a reproduction of the source analog signal.

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Munich, Germany

Stefan Ott